ISL1801 Datasheet, PDF (18/30 Pages) Intersil Corporation – sPMIC for Micro Converter Bias and Drivers

ISL1801
OVERVOLTAGE PROTECTION
The feedback voltage for VR1 and VR2 is continuously monitored
to prevent the output voltage from going too high.
When the VR1 output voltage feedback FB1 is higher than 120%
of VREF1, the Overvoltage Protection (OVP) is triggered. When
this condition occurs, the lower-side MOSFET of VR1 is turned on
immediately. At the same time, the preload current will be
applied to V_OUT1 to discharge the output. When the current
through the lower side MOSFET drops to 0, turn off this MOSFET
to prevent the negative inductor current. the OVP is reset when
FB1 voltage drops to VREF1.
For low voltage VR2, OVP is triggered when the FB2 voltage is
above 0.775V. When this condition occurs, the lower
synchronous MOSFET of VR2 is turned on immediately. It is held
on until the FB2 voltage drops below 0.73V.
POWER-GOOD SIGNAL (PGOOD2)
Both VR1 and VR2 have their own power-good signals to indicate
that their output voltage is within the regulation window. Only the
VR2 power-good signal is externally available at the PGOOD2 pin.
VR1’s power-good signal is used internally and is not available on
an external pin.
The PGOOD2 pin is a true open drain output. The power-good
comparator continuously monitors the feedback voltage FB2 for
an undervoltage condition. PGOOD2 is active low during
shutdown or when FB2 is below the threshold voltage. When the
FB2 voltage goes above 88% of its reference voltage
(0.88 * 0.73V = 0.64V), PGOOD2 is released and the pin will be a
high impedance.
The PGOOD2 signal can be used to reset the MCU powered by the
output of VR2.
The watchdog timer will also pull PGOOD2 low when a timeout
occurs. Please refer to “WatchDog Timer” on page 20 for more
information.
Dual LDO Bias Supplies
There are two LDOs in the ISL1801 to manage start-up and
power internal control circuitry.
The high voltage LDO1 can be directly connected to an input power
source up to 90V. Its output is connected to the VCC1 pin and is
typically about 6.7V. VCC1 provides the bias voltage for the power
stage of high voltage regulator. Typically, the VCC1 pin should be
connected to V_OUT1, the output of high voltage regulator VR1.
Before VR1 starts to operate, LDO1 can charge up the capacitor at
VCC1 when it is tied to V_OUT1. When the V_OUT1/VCC1 voltage
reaches 6.5V, VR1 starts to operate and will ramp V_OUT1/VCC1 to
a higher voltage. Once the VCC1 voltage is above 6.7V, LDO1 is
disabled. LDO1 limits its output current to 10mA.
There is a second low voltage LDO2 which can be connected to
inputs up to 14V. LDO2’s 5V output is connected to the VCC5V pin.
Typically, LDO2 is connected to the input voltage of low voltage
VR2 (typically V_OUT1). LDO2 supplies power for internal circuitry
such as the current sense Op amp, logic circuits, comparators and
the VR2 control circuits. One 2.2µF capacitor is recommended at
the VCC5V pin. LDO2 limits its output current to 10mA.
Dual Low-Side MOSFET Drivers
The ISL1801 has two low-side drivers for power MOSFETs
connected to the DRIVE3 and BDRIVE pins. Their high output
current enables them to rapidly charge and discharge the gate
capacitance of power MOSFETs. Both drivers are powered by the
PVCC3 pin, and each driver has its own ground pin. PGND3 is the
ground connection for DRIVE3 and PGND4 is the ground
connection for BDRIVE. The gate drivers (DRIVE3 and BDRIVE)
are always pull-down to ground by internal 14kΩ resistor.
Additional 250Ω pull-down resistor is available only after the 5V
LDO VCC5V has come up higher than 3.2V.
DRIVE3 CONTROL LOGIC
DRIVE3 is controlled by the PWM3 signal. When PWM3 = 1, the
DRIVE3 output is connected to PVCC3 by its upper switch. When
PWM3 = 0, DRIVE3 is connected to PGND3 through its lower
switch. However there are other logic signals which influence the
state of DRIVE3.
Before Power On Reset (POR) DRIVE3 is forced low. When the
output of comparator 1 (CMP1O) or comparator 2 (CMP2O) is
high it triggers a flip-flop (FF1) setting the open drain latch report
(LATCHRPT) signal low. It also connects DRIVE3 to PGND3
immediately. The RPWM3 pin has to be forced low to reset this
condition. Since the set input of flip-flop FF1 overrides the reset
input, DRIVE3 is always held low when CMP1O or CMP2O is high
even when RPWM3 = 0.
DRIVE3 OVERCURRENT LIMITING
A comparator monitors the PHASE3 voltage when DRIVE3 is high
to detect a possible overcurrent condition. When this comparator
output is high, DRIVE3 is immediately connected to PGND3. This
action provides overcurrent protection (OCP) for the power stage
driven by DRIVE3. Figure 18 shows the block diagram of the
PHASE3 OCP function.
The PHASE3 overcurrent limiting level is defined by the OCSET3 pin.
A 120µA current is supplied by the OCSET3 pin. Placing a resistor
from the OCSET3 pin to PGND3 sets the overcurrent threshold
voltage. A capacitor may be placed in parallel with the OCSET3
resistor to filter noise and provide a more consistent OCP threshold.
When DRIVE3 = 1, the internal switch S3 is turned on feeding the
PHASE3 signal to the OCP comparator. The PHASE3 voltage is
equal to the product of the current I1 and the conduction
resistance r_DS(ON) of the power MOSFET Q1. When the PHASE3
pin voltage is higher than the OCSET3 pin voltage, the DRIVE3
OCP is triggered. The overcurrent limiting level is:
I_OC3 = ¹----²-_r--_D⁰----^_S----^A_--_O---^--_N-^R---_--¹--
(EQ. 7)
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FN8259.1
July 24, 2014