ISL6353 Datasheet, PDF (29/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
Layout Guidelines (Continued)
ISL6353
PIN NUMBER
23
24, 25
26
27
29
30
31
32, 33
34
35
40
SYMBOL
BOOT1
UG1, PH1
GND
LG1
VDDP
LG2
GND
PH2, UG2
BOOT2
PROG2
ADDR
LAYOUT GUIDELINES
Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.
Run these two traces in parallel with fairly wide traces (>30mil). Avoid routing or crossing any sensitive analog signals
near this trace. Recommend routing the PH1 trace to the phase 1 high-side MOSFET source pins instead of general
copper.
Connect this pin to ground right next to the controller or to the exposed pad underneath the controller.
Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.
Place the decoupling capacitor a close as possible to this pin.
Use a fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.
Connect this pin to ground right next to the controller or to the exposed pad underneath the controller.
Run these two traces in parallel with fairly wide traces (>30mil). Avoid routing or crossing any sensitive analog signals
near this trace. Recommend routing the PH1 trace to the phase 1 high-side MOSFET source pins instead of general
copper.
Use fairly wide trace (>30mil). Avoid routing or crossing any sensitive analog signals near this trace.
Place resistor close to the controller.
Place resistor close to the controller.
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make
sure you have the latest Rev.
DATE
REVISION
CHANGE
09/15/2011
FN6897.0 Initial Release.
Products
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29
September 15, 2011
FN6897.0