ISL6353 Datasheet, PDF (23/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
too fast, the controller will limit the voltage slew rate at the
SetVID_slow slew rate.
ALERT# will be asserted low at the end of SetVID_fast and
SetVID_slow VID transitions.
When the ISL6353 is in DE mode, it will actively drive the output
voltage up when the VID changes to a higher value. DE operation
will resume after reaching the new voltage level. If the load is
light enough to warrant DCM, it will enter DCM after the inductor
current has crossed zero for four consecutive cycles. The ISL6353
will remain in DE mode when the VID changes to a lower value.
The output voltage will decay to the new value and the load will
determine the slew rate.
Protection Functions
The ISL6353 provides overcurrent, current-balance, overvoltage,
and over-temperature protection.
OVERCURRENT PROTECTION
The ISL6353 determines overcurrent protection (OCP) by
comparing the average value of the measured current I_sense with
an internal current source threshold. ISL6353 declares OCP when
I_sense is above the threshold for 120µs.
The way-overcurrent protection threshold is significantly above
the standard overcurrent protection threshold. The
way-overcurrent function is intended to provide a fast overcurrent
detection and action mechanism in a short circuit output
condition. Once the way-overcurrent condition is detected, the
PWM outputs will immediately shut off and PGOOD will go low to
maximize protection.
CURRENT BALANCE FAULT
The ISL6353 monitors the ISEN pin voltages to detect severe
phase current imbalances. If any ISEN pin voltage is more than
20mV different than the average ISEN voltage for 1ms, the
controller will declare a fault and latch off.
OVERVOLTAGE PROTECTION
The ISL6353 will declare an OVP fault if the output voltage
exceeds 175mV above the VID set value + positive offset. In the
event of an OVP condition, the OVP pin is pulled high. OVP is
blanked during dynamic VID events to prevent false trigger.
During soft-start, the OVP threshold is set at 2.33V to avoid a
false trigger due to turn on into a precharged output capacitor
bank.
POWER GOOD INDICATOR
The ISL6353 takes the same actions for all of the above fault
protection functions: PGOOD is set low and the high-side and low-
side MOSFETs are turned off. Any residual inductor current will
decay through the MOSFET body diodes. These fault conditions
can be reset by bringing VR_ON low or by bringing V_DD below the
POR threshold. When VR_ON and V_DD return to their high
operating levels, a soft-start will occur.
THERMAL MONITOR
The ISL6353 has a thermal throttling feature. If the voltage on
the NTC pin goes below the 0.91V threshold, the VR_HOT# pin is
pulled low indicating the need for thermal throttling to the
system. The VR_HOT# pin will be pulled back high if the voltage
on the NTC pin goes above 0.95V.
If the voltage on the NTC pin goes below 0.93V the ALERT# pin
will be pulled low indicating a thermal alert. ALERT# is reset by
checking the status register. ALERT# will be pulled low again if
the NTC pin voltage goes above 0.97V.
All the above fault conditions can be reset by bringing VR_ON low
or by bringing V_DD below the POR threshold. When VR_ON and
V_DD return to their high operating levels, a soft-start will occur.
VR_HOT#/ALERT# BEHAVIOR
Temp Zone
Bit 7 =1
Bit 6 =1
Bit 5 =1
VR Temperature
7
3% Hysteris
1111 1111
1
10
0111 1111
0011 1111
12 0001 1111
Temp Zone
Register
2
8
0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111
Status 1
Register ^{= “001”}
3
= “011”
5 _GerReg
= “001”
13 15 _GerReg
SVID
Status1
Status1
ALERT#
4
6
14 16
VR_HOT#
9
11
FIGURE 14. VR_HOT#/ALERT# BEHAVIOR
The controller drives a 60µA current source out of the NTC pin.
The current source flows through the NTC resistor network on the
pin and creates a voltage that is monitored by the controller
through an A/D converter (ADC) to generate the Tzone value.
Table 4 shows the typical programming table for Tzone. The user
needs to scale the NTC a network resistance such that it
generates the NTC pin voltage that corresponds to the left-most
column.
VNTC (V)
0.86
0.88
0.92
0.96
1.00
1.04
1.08
1.12
1.16
1.20
>1.20
TABLE 4. TZONE TABLE
TMAX (%)
>100
100
97
94
91
88
85
82
79
76
<76
TZONE
FFh
FFh
7Fh
3Fh
1Fh
0Fh
07h
03h
01h
01h
00h
23
September 15, 2011
FN6897.0