ISL6353 Datasheet, PDF (27/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
TABLE 11. SUPPORTED DATA AND CONFIGURATION
REGISTERS (Continued)
REGISTER
INDEX
NAME
DESCRIPTION
DEFAULT
VALUE
26h Vboot
If programmed by the platform, Refer to
the VR supports V_BOOT voltage Table 6
during start-up ramp. The VR
will ramp to V_BOOT and hold at
V_BOOT until it receives a new
SetVID command to move to a
different voltage.
30h Vout max
This register is programmed by FBh
the master and sets the
maximum VID the VR will
support. If a higher VID code is
received, the VR will respond
with “not supported”
acknowledge.
31h VID Setting Data register containing
00h
currently programmed VID
voltage. VID data format.
32h Power State Register containing the
00h
programmed power state.
33h Voltage Offset Sets offset in VID steps added to 00h
the VID setting for voltage
margining. Bit 7 is a sign bit,
0 = positive margin,
1 = negative margin.
Remaining 7 bits are # VID
steps for the margin.
00h = no margin,
01h = +1 VID step
02h = +2 VID steps...
34h Multi VR
Config
Data register that configures
multiple VRs behavior on the
same SVID bus.
VR1: 00h
VR2: 01h
Layout Guidelines
ISL6353
PIN NUMBER
SYMBOL
LAYOUT GUIDELINES
BOTTOM PAD
GND
Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to connect
to ground planes in PCB internal layers.
1, 2, 3
SDA,
ALERT#,
SCLK
Follow Intel recommendations.
4, 5, 6, 7, 22,
28, 36, 37, 38,
39
VR_ON,
PGOOD,
IMON,
VR_HOT#,
PROG1,
PWM3, PSI,
VSET1,
VSET2, OVP
No special consideration.
8
NTC
The NTC thermistor needs to be placed close to the thermal source that is monitored to determine the desired VR_HOT#
and thermal ALERT# toggling. Recommend placing it at the hottest spot of the ISL6353 based regulator.
9
VW
Place the resistor and capacitor from VW to COMP in close proximity of the controller.
27
September 15, 2011
FN6897.0