ISL6353 Datasheet, PDF (13/30 Pages) Intersil Corporation – Multiphase PWM Regulator for VR12 DDR Memory Systems

ISL6353
CCM/DCM BOUNDARY
VW
V_crs
iL
VW ^{LIGHT DCM}
Vcrs
iL
DEEP DCM
V_crs
VW
iL
FIGURE 7. PERIOD STRETCHING
Figure 7 shows the principle of operation in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size and therefore it is the same, making the inductor
current triangle the same in the three cases. The ISL6353 clamps
the ripple capacitor voltage V_crs in DE mode to make it mimic the
inductor current. It takes the COMP voltage longer to hit V_crs,
naturally stretching the switching period. The inductor current
triangles move further apart from each other such that the
inductor current average value is equal to the load current. The
reduced switching frequency helps increase light load efficiency.
Start-up Timing
With the controller's V_DD voltage above the POR threshold, the
start-up sequence begins about 1.3ms after VR_ON exceeds the
logic high threshold. The ISL6353 uses digital soft-start to ramp
up the DAC to the boot voltage, V_BOOT. V_BOOT is set by the PROG2
pin resistor and the status of the VSET1/2 pins. The DAC slew
rate during soft-start is about 2.5mV/µs. PGOOD is asserted high
at the end of the start-up sequence indicating that the output
voltage has moved to the V_BOOT setting, the VR is operating
properly and all phases are switching. Figure 8 shows the typical
start-up timing.
VDD
VR_ON
DAC
PGOOD
1.3ms
2.5mV/µs
VBOOT
READY FOR SVID COMMAND
FIGURE 8. SOFT-START WAVEFORMS
Voltage Regulation and Differential Sensing
After the start sequence, the ISL6353 regulates the output voltage
to the value set by the SetVID commands through the SVID bus or
to the value set by the status of the VSET1/2 pins. The ISL6353
will regulate the output voltage to VID + OFFSET (Register 33h). A
differential amplifier allows remote voltage sensing for precise
voltage regulation.
VID Table
The ISL6353 will regulate the output voltage to VID+OFFSET (33h).
Table 1 shows the output voltage setting based on the VID register
setting.
TABLE 1. VID TABLE
V_O
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Hex
(V)
0 0 0 0 0 0 0 0 0 0 0.0000
0 0 0 0 0 0 0 1 0 1 0.2500
0 0 0 0 0 0 1 0 0 2 0.2550
0 0 0 0 0 0 1 1 0 3 0.2600
0 0 0 0 0 1 0 0 0 4 0.2650
0 0 0 0 0 1 0 1 0 5 0.2700
0 0 0 0 0 1 1 0 0 6 0.2750
0 0 0 0 0 1 1 1 0 7 0.2800
0 0 0 0 1 0 0 0 0 8 0.2850
0 0 0 0 1 0 0 1 0 9 0.2900
0 0 0 0 1 0 1 0 0 A 0.2950
0 0 0 0 1 0 1 1 0 B 0.3000
0 0 0 0 1 1 0 0 0 C 0.3050
0 0 0 0 1 1 0 1 0 D 0.3100
0 0 0 0 1 1 1 0 0 E 0.3150
0 0 0 0 1 1 1 1 0 F 0.3200
0 0 0 1 0 0 0 0 1 0 0.3250
0 0 0 1 0 0 0 1 1 1 0.3300
0 0 0 1 0 0 1 0 1 2 0.3350
0 0 0 1 0 0 1 1 1 3 0.3400
0 0 0 1 0 1 0 0 1 4 0.3450
0 0 0 1 0 1 0 1 1 5 0.3500
13
September 15, 2011
FN6897.0