ISL6306 Datasheet, PDF (29/33 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6306
Case 1:
Case 2:
---------1----------
2π LC
>
f₀
R_C
=
R_F
B
2----π_{----f--0---V-----P------P--------L----C---}
0.75 V _{I N}
C_C = _2----π----V-0---._P--7--_--5-_P---V-R---^I-_F-^N---_B----f--₀-
---------1----------
2π LC
≤
f₀
<
-2---_π----C-----₍-1-E-----S----R-----₎
R_C
=
R_F
B
V-----_P------P----(_---2----π_---)_---²_----f--0--²_----L----C--
0.75 V_IN
C_C
=
---------------------0----.-7----5---V-----^I-^N-----------------------
(2π)² f₀₂ V_P-PR_FB LC
(EQ. 33)
Case 3:
f₀ > _2----π----C-----₍-1-E-----S----R-----₎
R_C
=
R_FB
------2----^π-----f--⁰---V----^P----^---^P----L-------
0.75 V_IN (ESR)
C_C
=
0----.--7---5----V----_I--N----(_{--E-----S----R-----})_-------C---
2πV_P-PR_FBf₀ L
In Equation 33, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_PP is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
“Electrical Specifications” on page 8.
The optional capacitor C₂, is sometimes needed to bypass
noise away from the PWM comparator (see Figure 20). Keep
a position available for C₂, and be prepared to install a high-
frequency capacitor of between 22pF and 150pF in case any
leading-edge jitter problem is noted.
Once selected, the compensation values in Equation 33
assure a stable converter with reasonable transient
performance. In most cases, transient performance can be
improved by making adjustments to R_C. Slowly increase the
value of R_C while observing the transient performance on an
oscilloscope until no further improvement is noted. Normally,
C_C will not need adjustment. Keep the value of C_C from
Equation 33 unless some performance issue is noted.
COMPENSATION WITHOUT LOAD-LINE REGULATION
The non load-line regulated converter is accurately modeled
as a voltage-mode regulator with two poles at the LC
resonant frequency and a zero at the ESR frequency. A
type III controller, as shown in Figure 20, provides the
necessary compensation.
29
C₂
R_C ^CC
COMP
FB
C₁
R₁
R_FB
IDROOP
VDIFF
FIGURE 20. COMPENSATION CIRCUIT FOR ISL6306 BASED
CONVERTER WITHOUT LOAD-LINE
REGULATION
The first step is to choose the desired bandwidth, f₀, of the
compensated system. Choose a frequency high enough to
assure adequate transient performance but not higher than
1/3 of the switching frequency. The type-III compensator has
an extra high-frequency pole, f_HF. This pole can be used for
added noise rejection or to assure adequate attenuation at
the error-amplifier high-order pole and zero frequencies. A
good general rule is to choose f_HF = 10f₀, but it can be
higher if desired. Choosing f_HF to be lower than 10f₀ can
cause problems with too much phase shift below the system
bandwidth.
In the solutions to the compensation equations, there is a
single degree of freedom. For the solutions presented in
Equation 34, R_FB is selected arbitrarily. The remaining
compensation components are then selected according to
Equation 34.
R₁
=
R_F
B
----------C----⁽---E----S-----R-----⁾---------
LC – C(ESR)
C₁
=
-----L---C------^–-----C-----⁽--E-----S----R-----⁾
R_FB
C₂
=
------------------------0---.--7---5----V----^I--^N--------------------------
(2π)²f₀f_HF LCR_FBV_P-P
R_C
=
---V----^P----^---^P---^⎝⎛---2----^π---^⎠⎞---²----f--⁰---f--^H----^F----L---C-----R-----^F---^B----
0.75 V_{IN ⎝⎛}2πf_HF LC–1_⎠⎞
C_C
=
---0----.-7----5---V-----^I--^N----^⎝⎛-2----^π----f--^H----^F--------L----C----^–----1---^⎠⎞----
(2π)²f₀f_HF LCR_FBV_P-P
(EQ. 34)
In Equation 34, L is the per-channel filter inductance divided
by the number of active channels; C is the sum total of all
output capacitors; ESR is the equivalent-series resistance of
the bulk output-filter capacitance; and V_P-P is the peak-to-
peak sawtooth signal amplitude as described in Figure 7 and
“Electrical Specifications” on page 8.
FN9226.1
May 5, 2008