ISL6306 Datasheet, PDF (23/33 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6306
During TD2 and TD4, ISL6306 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R_ss from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on Equations 15 and 16:
TD2 = ^{1----.--1---x----R----S}----^S-- (μs)
6.25 x 25
(EQ. 15)
TD4
=
(_{---V----V----I--D-----}–_{-----1---.--1----})_{--x---R-----S----S--}
6.25 x 25
(μs)
(EQ. 16)
For example, when VID is set to 1.5V and the Rss is set at
100kΩ, the first soft-start ramp time TD2 will be 704µs and
the second soft-start ramp time TD4 will be 256µs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay TD5. The
typical value for TD5 is 85µs.
VOUT, 500mV/DIV
TD1
TD2 TD3 TD4 TD5
EN_VTT
VR_REDY
500µs/DIV
FIGURE 11. SOFT-START WAVEFORMS
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at V_SEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6306
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the second soft-start, the OVP threshold is 1.275V. Once the
controller detects valid VID input, the OVP trip point will be
changed to VID plus 175mV.
Two actions are taken by the ISL6306 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns) until the
voltage at VDIFF falls below 0.4V. This causes the Intersil
drivers to turn on the lower MOSFETs and pull the output
voltage below a level that might cause damage to the load.
The PWM outputs remain low until VDIFF falls below 0.4V,
and then PWM signals enter a high-impedance state. The
Intersil drivers respond to the high-impedance input by
turning off both upper and lower MOSFETs. If the
overvoltage condition reoccurs, the ISL6306 will again
command the lower MOSFETs to turn on. The ISL6306 will
continue to protect the load in this fashion as long as the
overvoltage condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6306 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the POR-
falling threshold will reset the controller. Cycling the VID
codes will not reset the controller.
Fault Monitoring and Protection
The ISL6306 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
external system monitors. The schematic in Figure 12
outlines the interaction between the fault monitors and the
VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fixed delay TD5. VR_RDY will be pulled low when an
undervoltage or overvoltage condition is detected, or the
controller is disabled by a reset from EN_PWR, EN_VTT,
POR, or VID OFF-code.
VR_RDY
UV
50%
DAC
DELAY
-
OC
+
100µA
I₁
REPEAT FOR
EACH CHANNEL
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
100µA
I_AVG
V_DIFF
+
OV
-
VID + 0.175V
FIGURE 12. VR_RDY AND PROTECTION CIRCUITRY
23
FN9226.1
May 5, 2008