ISL6306 Datasheet, PDF (22/33 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6306
The ISL6306 checks the VID inputs six times every switching
cycle. If the VID code is found to have been changed, the
controller waits for half of a switching cycle before executing a
6.25mV step change. If the difference between DAC level and
the new VID code changes during the half-cycle waiting period,
no change to the DAC output is made. If the VID code is more
than 1 bit higher or lower than the DAC (not recommended),
the controller will execute 6.26mV step change six times per
cycle until VID and DAC are equal. Therefore it is important to
carefully control the rate of VID stepping in 1-bit increments.
In order to ensure the smooth transition of output voltage during
VID change, a VID step change smoothing network, composed
of R_REF and C_REF, can be used. The selection of R_REF is
based on the desired offset voltage as detailed in “Output-
Voltage Offset Programming” on page 21. The selection of
C_REF is based on the time duration for 1 bit VID change and
the allowable delay time.
Assuming the microprocessor controls the VID change at 1-bit
every T_VID, the relationship between the time constant of R_REF
and C_REF network and T_VID is given by Equation 13.
C_REF R_REF = T_VID
(EQ. 13)
Operation Initialization
Prior to converter initialization, proper conditions must exist on
the enable inputs and VCC. When the conditions are met, the
controller begins soft-start. Once the output voltage is within the
proper window of operation, VR_RDY asserts logic high.
ISL6306 INTERNAL CIRCUIT EXTERNAL CIRCUIT
V_CC
+12V
POR
CIRCUIT
ENABLE
COMPARATOR
+
-
0.875V
10kΩ
EN_PWR
910Ω
+
EN_VTT
-
SOFT-START
AND
FAULT LOGIC
0.875V
FIGURE 10. POWER SEQUENCING USING THRESHOLD-
SENSITIVE ENABLE (EN) FUNCTION
Enable and Disable
While in shutdown mode, the PWM outputs are held in a
high-impedance state to assure the drivers remain off. The
following input conditions must be met before the ISL6306 is
released from shutdown mode.
1. The bias voltage applied at VCC must reach the internal
power-on reset (POR) rising threshold. Once this
threshold is reached, proper operation of all aspects of
the ISL6306 is guaranteed. Hysteresis between the rising
and falling thresholds assure that once enabled, the
ISL6306 will not inadvertently turn off unless the bias
voltage drops substantially (see “Electrical
Specifications” on page 8).
2. The ISL6306 features an enable input (EN_PWR) for
power sequencing between the controller bias voltage
and another voltage rail. The enable comparator holds
the ISL6306 in shutdown until the voltage at EN_PWR
rises above 0.875V. The enable comparator has about
130mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their POR level before the
ISL6306 becomes enabled. The schematic in Figure 10
demonstrates sequencing the ISL6306 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V
bias.
3. The voltage on EN_VTT must be higher than 0.875V to
enable the controller. This pin is typically connected to the
output of VTT VR.
When all conditions above are satisfied, ISL6306 begins the
soft-start and ramps the output voltage to 1.1V first. After
remaining at 1.1V for some time, ISL6306 reads the VID
code at VID input pins. If the VID code is valid, ISL6306 will
regulate the output to the final VID setting. If the VID code is
OFF code, ISL6306 will shut down, and cycling VCC,
EN_PWR or EN_VTT is needed to restart.
Soft-Start
ISL6306 based VR has 4 periods during soft-start as shown
in Figure 11. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, The controller will have fixed delay
period TD1. After this delay period, the VR will begin first
soft-start ramp until the output voltage reaches 1.1V V_BOOT
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period TD3. At the end of TD3 period,
ISL6306 reads the VID signals. If the VID code is valid,
ISL6306 will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
The soft-start time is the sum of the 4 periods as shown in
Equation 14.
T_SS = TD1 + TD2 + TD3 + TD4
(EQ. 14)
TD1 is a fixed delay with the typical value as 1.36ms. TD3 is
determined by the fixed 85µs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum TD3 is about 86µs.
22
FN9226.1
May 5, 2008