ISL6306 Datasheet, PDF (13/33 Pages) Intersil Corporation – 4-Phase PWM Controller with 8-Bit DAC Code Capable of Precision rDS ON or DCR Differential Current Sensing

ISL6306
IL1 + IL2 + IL3, 7A/DIV
IL1, 7A/DIV
PWM1, 5V/DIV
IL2, 7A/DIV
IL3, 7A/DIV
PWM2, 5V/DIV
PWM3, 5V/DIV
1µs/DIV
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
FOR 3-PHASE CONVERTER
To understand the reduction of ripple current amplitude in the
multiphase circuit, examine Equation 1 which represents an
individual channel’s peak-to-peak inductor current.
I_{P-P =}
(_{---V----I--N-----}–_{-----V----O-----U----T---})_{----V----O----U-----T-}
L f_S V_IN
(EQ. 1)
In Equation 1, V_IN and V_OUT are the input and output
voltages respectively, L is the single-channel inductor value,
and f_S is the switching frequency.
INPUT-CAPACITOR CURRENT, 10A/DIV
CHANNEL 1
INPUT CURRENT
10A/DIV
CHANNEL 2
INPUT CURRENT
10A/DIV
CHANNEL 3
INPUT CURRENT
10A/DIV
1µs/DIV
FIGURE 2. CHANNEL INPUT CURRENTS AND INPUT-
CAPACITOR RMS CURRENT FOR THREE-PHASE
CONVERTER
The output capacitors conduct the ripple component of the
inductor current. In the case of multiphase converters, the
capacitor current is the sum of the ripple currents from each of
the individual channels. Compare Equation 1 to the expression
for the peak-to-peak current after the summation of N
symmetrically phase-shifted inductor currents in Equation 2.
Peak-to-peak ripple current decreases by an amount
proportional to the number of channels. Output voltage ripple is
a function of capacitance, capacitor equivalent series
resistance (ESR), and inductor ripple current. Reducing the
inductor ripple current allows the designer to use fewer or less
costly output capacitors.
13
I_{C, P-P}=
(_{---V----I--N-----}–_{-----N------V----O-----U----T---})_{----V----O----U-----T-}
L
f_S
V
I
N
(EQ. 2)
Another benefit of interleaving is to reduce input ripple
current. Input capacitance is determined in part by the
maximum input ripple current. Multiphase topologies can
improve overall system cost and size by lowering input ripple
current and allowing the designer to reduce the cost of input
capacitance. The example in Figure 2 illustrates input
currents from a 3-phase converter combining to reduce the
total input ripple current.
The converter depicted in Figure 2 delivers 36A to a 1.5V load
from a 12V input. The RMS input capacitor current is 5.9A.
Compare this to a single-phase converter also stepping down
12V to 1.5V at 36A. The single-phase converter has 11.9A
RMS input capacitor current. The single-phase converter
must use an input capacitor bank with twice the RMS current
capacity as the equivalent 3-phase converter.
Figures 21, 22 and 23 in the section entitled “Input Capacitor
Selection” on page 30, can be used to determine the input-
capacitor RMS current based on load current, duty cycle,
and the number of channels. They are provided as aids in
determining the optimal input capacitor solution. Figure 23
shows the single-phase input-capacitor RMS current for
comparison.
PWM Operation
The timing of each channel is set by the number of active
channels. The default channel setting for the ISL6306 is four.
The switching cycle is defined as the time between PWM
pulse termination signals of each channel. The pulse
termination signal is an internally generated clock signal
which triggers the falling edge of PWM signal. The cycle time
of the pulse termination signal is the inverse of the switching
frequency set by the resistor between the FS pin and
ground. Each cycle begins when the clock signal commands
the channel PWM signal to go low. The PWM signals
command the MOSFET driver to turn on/off the channel
MOSFETs.
For 4-channel operation, the channel firing order is 4-3-2-1:
PWM3 pulse terminates 1/4 of a cycle after PWM4, PWM2
output follows another 1/4 of a cycle after PWM3, and
PWM1 terminates another 1/4 of a cycle after PWM2. For
3-channel operation, the channel firing order is 3-2-1.
Connecting PWM4 to VCC selects three channel operation
and the pulse-termination times are spaced in 1/3 cycle
increments. If PWM3 is connected to VCC, two channel
operation is selected and the PWM2 pulse terminates 1/2 of
a cycle later.
Once a PWM signal transitions low, it is held low for a
minimum of 1/3 cycle. This forced off time is required to
ensure an accurate current sample. Current sensing is
described in the next section. After the forced off time
expires, the PWM output is enabled. The PWM output state
FN9226.1
May 5, 2008