80C88 Datasheet, PDF (25/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Waveforms (Continued)
V_CC
≥ 50µs
CLK
(7) TCLDX1
(6) TDVCL
RESET
≥ 4 CLK CYCLES
FIGURE 30. RESET TIMING
AC Test Circuit
OUTPUT FROM
DEVICE UNDER TEST
TEST
POINT
CL (NOTE)
NOTE: Includes stay and jig capacitance.
AC Testing Input, Output Waveform
INPUT
V_IH + 20% V_IH
1.5V
V_IL - 50% V_IL
OUTPUT
1.5V
V_OH
V_OL
AC Testing: All input signals (other than CLK) must switch between
V_ILMAX -50% V_IL and V_IHMIN +20% V_IH. CLK must
switch between 0.4V and V_CC -0.4V. Input rise and fall
times are driven at 1ns/V.
Burn-In Circuits
GND
RIO
GND
RIO
VCL
RIO
GND
RIO
GND
RIO
VCL
RIO
GND
RIO
GND
RIO
GND
RIO
VCL
RIO
VCL
RIO
VCL
OPEN
OPEN
OPEN
OPEN
GND
GND
RC
F0
GND
MD80C88 (CERDIP)
1 GND
2 A14
3 A13
4 A12
5 A11
6 A10
7 A9
8 A8
9 AD7
10 AD6
11 AD5
12 AD4
13 AD3
14 AD2
15 AD1
16 AD0
17 NMI
18 INTR
19 CLK
20 GND
V_CC 40
A15 39
A16 38
A17 37
A18 36
A19 35
BHE 34
MX 33
RD 32
RQ0 31
RQ1 30
LOCK 29
S2 28
S1 27
S0 26
QS0 25
QS2 24
TEST ²³
READY ²²
RESET ²¹
C
GND
V_CC
RIO
VCL
RO
VCC/2
RO
VCC/2
RO
VCC/2
RO
VCC/2
RO
VCC/2
GND
RO
VIL
RI
VCL
RO
VCL
RO
VCC/2
RO
VCC/2
RO
VCC/2
RO _VCC/2
RO
VCC/2
RO
VCC/2
GND
RI _VCL
RI
NODE
FROM
A
PROGRAM
CARD
3-25