80C88 Datasheet, PDF (22/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Waveforms
CLK
(23)
TCLAV
QS0, QS1
(21) TCHSV
S2, S1, S0 (EXCEPT HALT)
T1
(1)
TCLCL
(4) ^T2
TCH1CH2
TCHCL (3)
T3
T4
(5)
TCL2CL1 TW
TCLCH
(2)
(22) ^TCLSH
(SEE NOTE 20)
A15-A8
(23) TCLAV
A19/S6-A16/S3
TSVLH
(27)
ALE (82C88 OUTPUT)
TCLLH
(29)
NOTES 18, 19
TCLDV
TCLAX
A19-A16
TCHLL ⁽³¹⁾
A15-A8
(33)
(24)
TR1VCL
(8)
S6-S3
(23)
TCLAV
RDY (82C84 INPUT)
READY 80C86 INPUT)
READ CYCLE
TCLAV
(23)
AD7-AD0
RD
(41) TCHDTL
DT/R
TCLR1X
(9)
(12) TRYLCL
(24)
TCLAX
(25)
TCLAZ
TRYHSH
(20)
TRYHCH
(10)
(6)
TDVCL
(11)
TCHRYX
(7)
TCLDX1
AD7-AD0
DATA IN
(37) TAZRL
(39) TCLRH
TRHAV
(40)
TCLRL
(38)
TRLRH
(45)
(42)
TCHDTH
82C88
OUTPUTS
SEE NOTES 19, 21
MRDC OR IORC
DEN
TCLML
(18)
(35) TCVNV
TCLMH
(19)
TCVNX
(36)
NOTES:
FIGURE 24. BUS TIMING - MAXIMUM MODE (USING 82C88)
18. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.
19. Signals at 82C84A or 82C88 are shown for reference only.
20. Status inactive in state just prior to T4.
21. The issuance of the 82C88 command and control signals (MRDC, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active
high 82C88 CEN.
3-22