80C88 Datasheet, PDF (12/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
Non-Maskable Interrupt (NMI)
The processor provides a single non-maskable interrupt
(NMI) pin which has higher priority than the maskable
interrupt request (INTR) pin. A typical use would be to
activate a power failure routine. The NMI is edge-triggered
on a LOW to High transition. The activation of this pin
causes a type 2 interrupt.
NMI is required to have a duration in the HIGH state of
greater than two clock cycles, but is not required to be
synchronized to the clock. An high going transition of NMI is
latched on-chip and will be serviced at the end of the current
instruction or between whole moves (2 bytes in the case of
word moves) of a block type instruction. Worst case
response to NMI would be for multiply, divide, and variable
shift instructions. There is no specification on the occurrence
of the low-going edge; it may occur before, during, or after
the servicing of NMI. Another high-going edge triggers
another response if it occurs after the start of the NMI
procedure.
The signal must be free of logical spikes in general and be
free of bounces on the low-going edge to avoid triggering
extraneous responses.
Maskable Interrupt (INTR)
The 80C88 provides a singe interrupt request input (INTR)
which can be masked internally by software with the
resetting of the interrupt enable (IF) flag bit. The interrupt
request signal is level triggered. It is internally synchronized
during each clock cycle on the high-going edge of CLK.
To be responded to, INTR must be present (HIGH) during
the clock period preceding the end of the current instruction
or the end of a whole move for a block type instruction. INTR
may be removed anytime after the falling edge of the first
INTA signal. During interrupt response sequence, further
interrupts are disabled. The enable bit is reset as part of the
response to any interrupt (INTR, NMI, software interrupt, or
single step). The FLAGS register, which is automatically
pushed onto the stack, reflects the state of the processor
prior to the interrupt. The enable bit will be zero until the old
FLAGS register is restored, unless specifically set by an
instruction.
During the response sequence (see Figure 7), the processor
executes two successive (back-to-back) interrupt acknowl-
edge cycles. The 80C88 emits to LOCK signal (maximum
mode only) from T2 of the first bus cycle until T2 of the sec-
ond. A local bus “hold” request will not be honored until the
end of the second bus cycle. In the second bus cycle, a byte
is fetched from the external interrupt system (e.g., 82C59A
PIC) which identifies the source (type) of the interrupt. This
byte is multiplied by four and used as a pointer into the inter-
rupt vector lookup table.
An INTR signal left HIGH will be continually responded to
within the limitations of the enable bit and sample period.
INTR may be removed anytime after the falling edge of the
first INTA signal. The interrupt return instruction includes a
flags pop which returns the status of the original interrupt
enable bit when it restores the flags.
T1
T2 T3 T4
T1
ALE
T2 T3
T4
LOCK
INTA
AD0-
AD7
TYPE
VECTOR
FIGURE 20. INTERRUPT ACKNOWLEDGE SEQUENCE
Halt
When a software HALT instruction is executed, the proces-
sor indicates that it is entering the HALT state in one of two
ways, depending upon which mode is strapped. In minimum
mode, the processor issues ALE, delayed by one clock
cycle, to allow the system to latch the halt status. Halt status
is available on IO/M, DT/R, and SS0. In maximum mode, the
processor issues appropriate HALT status on S2, S1 and
S0, and the 82C88 bus controller issues one ALE. The
80C88 will not leave the HALT state when a local bus hold is
entered while in HALT. In this case, the processor reissues
the HALT indicator at the end of the local bus hold. An inter-
rupt request or RESET will force the 80C88 out of the HALT
state.
Read/Modify/Write (Semaphore) Operations Via LOCK
The LOCK status information is provided by the processor
when consecutive bus cycles are required during the execu-
tion of an instruction. This allows the processor to perform
read/modify/write operations on memory (via the “exchange
register with memory” instruction), without another system
bus master receiving intervening memory cycles. This is
useful in multiprocessor system configurations to accomplish
“test and set lock” operations. The LOCK signal is activated
(LOW) in the clock cycle following decoding of the LOCK
prefix instruction. It is deactivated at the end of the last bus
cycle of the instruction following the LOCK prefix. While
LOCK is active, a request on a RQ/GT pin will be recorded,
and then honored at the end of the LOCK.
External Synchronization Via TEST
As an alternative to interrupts, the 80C88 provides a single
software-testable input pin (TEST). This input is utilized by
executing a WAIT instruction. The single WAIT instruction is
repeatedly executed until the TEST input goes active (LOW).
The execution of WAIT does not consume bus cycles once
the queue is full.
If a local bus request occurs during WAIT execution, the
80C88 three-states all output drivers while inputs and I/O
pins are held at valid logic levels by internal bus-hold circuits.
If interrupts are enabled, the 80C88 will recognize interrupts
and process them when it regains control of the bus.
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