80C88 Datasheet, PDF (17/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
AC Electrical Specifications
MINIMUM COMPLEXITY SYSTEM
V_CC = 5.0V ±10%; T_A = 0^oC to +70^oC (C80C88, C80C88-2)
V_CC = 5.0V ±100%; T_A = -40^oC to +85^oC (I80C88, I80C88-2)
V_CC = 5.0V ±100%; T_A = -55^oC to +125^oC (M80C88)
V_CC = 5.0V ±5%; T_A = -55^oC to +125^oC (M80C88-2) (Continued)
SYMBOL
PARAMETER
80C88
MIN
MAX
80C88-2
MIN
MAX UNITS
TEST
CONDITIONS
(25) TLLAX Address Hold Time to ALE Inactive
TCHCL-10
-
TCHCL-10 -
ns CL = 100pF
(26) TCLDV Data Valid Delay
10
110
10
60
ns CL = 100pF
(27) TCLDX2 Data Hold Time
10
-
10
-
ns CL = 100pF
(28) TWHDX Data Hold Time After WR
TCLCL-30
-
TCLCL-30
-
ns CL = 100pF
(29) TCVCTV Control Active Delay 1
10
110
10
70
ns CL = 100pF
(30) TCHCTV Control Active Delay 2
10
110
10
60
ns CL = 100pF
(31) TCVCTX Control Inactive Delay
10
110
10
70
ns CL = 100pF
(32) TAZRL Address Float to READ Active
0
-
0
-
ns CL = 100pF
(33) TCLRL RD Active Delay
10
165
10
100
ns CL = 100pF
(34) TCLRH RD Inactive Delay
10
150
10
80
ns CL = 100pF
(35) TRHAV RD Inactive to Next Address Active
TCLCL-45
-
TCLCL-40
-
ns CL = 100pF
(36) TCLHAV HLDA Valid Delay
10
160
10
100
ns CL = 100pF
(37) TRLRH RD Width
2TCLCL-75
- 2TCLCL-50 -
ns CL = 100pF
(38) TWLWH WR Width
2TCLCL-60
- 2TCLCL-40 -
ns CL = 100pF
(39) TAVAL Address Valid to ALE Low
TCLCH-60
-
TCLCH-40
-
ns CL = 100pF
(40) TOLOH Output Rise Time
-
15
-
15
ns From 0.8V to 2.0V
(41) TOHOL Output Fall Time
-
15
-
15
ns From 2.0V to 0.8V
NOTES:
6. Signal at 82C84A shown for reference only.
7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.
8. Applies only to T2 state (8ns into T3).
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