80C88 Datasheet, PDF (16/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
AC Electrical Specifications
MINIMUM COMPLEXITY SYSTEM
V_CC = 5.0V ±10%; T_A = 0^oC to +70^oC (C80C88, C80C88-2)
V_CC = 5.0V ±100%; T_A = -40^oC to +85^oC (I80C88, I80C88-2)
V_CC = 5.0V ±100%; T_A = -55^oC to +125^oC (M80C88)
V_CC = 5.0V ±5%; T_A = -55^oC to +125^oC (M80C88-2)
SYMBOL
PARAMETER
80C88
MIN
MAX
80C88-2
MIN
MAX UNITS
TEST
CONDITIONS
TIMING REQUIREMENTS
(1) TCLCL CLK Cycle Period
200
-
125
-
ns
(2) TCLCH CLK Low Time
118
-
68
-
ns
(3) TCHCL CLK High Time
69
-
44
-
ns
(4) TCH1CH2 CLK Rise Time
-
10
-
10
ns From 1.0V to 3.5V
(5) TCL2CL1 CLK FaIl Time
-
10
-
10
ns From 3.5V to 1.0V
(6) TDVCL Data In Setup Time
30
-
20
-
ns
(7) TCLDX1 Data In Hold Time
10
-
10
-
ns
(8) TR1VCL RDY Setup Time into 82C84A
(Notes 6, 7)
35
-
35
-
ns
(9) TCLR1X RDY Hold Time into 82C84A
(Notes 6, 7)
0
-
0
-
ns
(10) TRYHCH READY Setup Time into 80C88
118
-
68
-
ns
(11) TCHRYX READY Hold Time into 80C88
30
-
20
-
ns
(12) TRYLCL READY Inactive to CLK (Note 8)
-8
-
-8
-
ns
(13) THVCH HOLD Setup Time
35
-
20
-
ns
(14) TINVCH lNTR, NMI, TEST Setup Time
(Note 7)
30
-
15
-
ns
(15) TILIH Input Rise Time (Except CLK)
-
15
-
15
ns From 0.8V to 2.0V
(16) TIHIL Input FaIl Time (Except CLK)
-
15
-
15
ns From 2.0V to 0.8V
TIMING RESPONSES
(17) TCLAV Address Valid Delay
10
110
10
60
ns CL = 100pF
(18) TCLAX Address Hold Time
10
-
10
-
ns CL = 100pF
(19) TCLAZ Address Float Delay
TCLAX
80
TCLAX
50
ns CL = 100pF
(20) TCHSZ Status Float Delay
-
80
-
50
ns CL = 100pF
(21) TCHSV Status Active Delay
10
110
10
60
ns CL = 100pF
(22) TLHLL ALE Width
TCLCH-20
-
TCLCH-10 -
ns CL = 100pF
(23) TCLLH ALE Active Delay
-
80
-
50
ns CL = 100pF
(24) TCHLL ALE Inactive Delay
-
85
-
55
ns CL = 100pF
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