80C88 Datasheet, PDF (20/32 Pages) Intersil Corporation – CMOS 8/16-Bit Microprocessor

80C88
AC Electrical Specifications
V_CC = 5.0V ±10%; T_A = 0^oC to +70^oC (C80C88, C80C88-2)
V_CC = 5.0V ±10%; T_A = -40^oC to +85^oC (I80C88, I80C88-2)
V_CC = 5.0V ±10%; T_A = -55^oC to +125^oC (M80C88)
V_CC = 5.0V ±5%; T_A = -55^oC to +125^oC (M80C88-2)
MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)
80C88
80C88-2
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX UNITS TEST CONDITIONS
TIMING REQUIREMENTS
(1) TCLCL CLK Cycle Period
200
-
125
-
ns
(2) TCLCH CLK Low Time
118
-
68
-
ns
(3) TCHCL CLK High Time
69
-
44
-
ns
(4) TCH1CH2 CLK Rise Time
-
10
-
10
ns From 1.0V to 3.5V
(5) TCL2CL1 CLK Fall Time
-
10
-
10
ns From 3.5V to 1.0V
(6) TDVCL Data in Setup Time
30
-
20
-
ns
(7) TCLDX1 Data In Hold Time
10
-
10
-
ns
(8) TR1VCL RDY Setup Time into 82C84
(Notes 13, 14)
35
-
35
-
ns
(9) TCLR1X RDY Hold Time into 82C84
(Notes 13, 14)
0
-
0
-
ns
(10) TRYHCH READY Setup Time into 80C88
118
-
68
-
ns
(11) TCHRYX READY Hold Time into 80C88
30
-
20
-
ns
(12) TRYLCL READY Inactive to CLK (Note 15)
-8
-
-8
-
ns
(13) TlNVCH Setup Time for Recognition (lNTR,
30
-
15
-
ns
NMl, TEST) (Note 14)
(14) TGVCH RQ/GT Setup Time
30
-
15
-
ns
(15) TCHGX RQ Hold Time into 80C88 (Note 16)
40 TCHCL+ 30 TCHCL+ ns
10
10
(16) TILlH Input Rise Time (Except CLK)
-
15
-
15
ns From 0.8V to 2.0V
(17) TIHIL Input Fall Time (Except CLK)
-
15
-
15
ns From 2.0V to 0.8V
TIMING RESPONSES
(18) TCLML Command Active Delay (Note 13)
5
35
5
35
ns
(19) TCLMH Command Inactive (Note 13)
5
35
5
35
ns
(20) TRYHSH READY Active to Status Passive
(Notes 15, 17)
-
110
-
65
ns
(21) TCHSV Status Active Delay
10
110
10
60
ns
(22) TCLSH Status Inactive Delay (Note 17)
10
130
10
70
ns
(23) TCLAV Address Valid Delay
(24) TCLAX Address Hold Time
(25) TCLAZ Address Float Delay
(26) TCHSZ Status Float Delay
10
110
10
60
10
-
10
-
TCLAX
80
TCLAX
50
-
80
-
50
ns _{CL = 100pF}
ns ^{for all 80C88 outputs}
in addition to internal
ns _loads.
ns
(27) TSVLH Status Valid to ALE High (Note 13)
-
20
-
20
ns
(28) TSVMCH Status Valid to MCE High (Note 13)
-
30
-
30
ns
(29) TCLLH CLK Low to ALE Valid (Note 13)
-
20
-
20
ns
(30) TCLMCH CLK Low to MCE High (Note 13)
-
25
-
25
ns
(31) TCHLL ALE Inactive Delay (Note 13)
4
18
4
18
ns
3-20