ISL6265 Datasheet, PDF (23/24 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

ISL6265
FB PINS
The input impedance of the FB pin is high, so place the
voltage programming and loop compensation components
close to the COMP, FB, and GND pins keeping the high
impedance trace short.
FSET_NB PIN
This pin requires a quiet environment. The resistor R_FSET
should be placed directly adjacent to this pin. Keep fast
moving nodes away from this pin.
LGATE ROUTING
The LGATE trace has a signal going through it that is both
high dV/dt and di/dt, with high peak charging and
discharging current. Route this trace in parallel with the trace
from the PGND pin. These two traces should be short, wide,
and away from other traces. There should be no other weak
signal traces in proximity with these traces on any layer.
BOOT AND PHASE ROUTING
The signals going through these traces are both high dv/dt
and high di/dt, with high peak charging and discharging
current. Route the UGATE and PHASE pins in parallel with
short and wide traces. There should be no other weak signal
traces in proximity with these traces on any layer.
Copper Size for the Phase Node
The parasitic capacitance and parasitic inductance of the
phase node should be kept very low to minimize ringing. It is
best to limit the size of the PHASE node copper in strict
accordance with the current and thermal management of the
application. An MLCC should be connected directly across
the drain of the upper MOSFET and the source of the lower
MOSFET to suppress the turn-off voltage.
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FN6599.1
May 13, 2009