ISL6265 Datasheet, PDF (11/24 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

ISL6265
output ripple and lower phase jitter than either conventional
hysteretic or fixed frequency PWM controllers. Unlike
conventional hysteretic converters, the ISL6265 has an error
amplifier that allows the controller to maintain a 0.5% voltage
regulation accuracy throughout the VID range from 0.75V to
1.55V. Voltage regulation accuracy is slightly wider, ±5mV,
over the VID range from 0.7375V to 0.5V.
The hysteresis window voltage is relative to the error
amplifier output such that load current transients result in
increased switching frequency, which gives the R³ regulator
a faster response than conventional fixed frequency PWM
controllers. In uniplane configurations, transient load current
is inherently shared between active phases due to the use of
a common hysteretic window voltage. Individual average
phase currents are monitored and controlled to equally
share current among the active phases.
Modulator
The ISL6265 modulator features Intersil’s R³ technology, a
hybrid of fixed frequency PWM control and variable
frequency hysteretic control (see Figure 5). Intersil’s R³
technology can simultaneously affect the PWM switching
frequency and PWM duty cycle in response to input voltage
and output load transients. The R³ modulator synthesizes an
AC signal V_R, which is an analog representation of the
output inductor ripple current. The duty-cycle of V_R is the
result of charge and discharge current through a ripple
capacitor C_R. The current through C_R is provided by a
transconductance amplifier g_m that measures the VIN and
VO voltages. The positive slope of V_R can be written as
determined by Equation 1:
V_RPOS = (g_m) ⋅ (V_IN – V_OUT)
(EQ. 1)
The negative slope of V_R can be written as determined by
Equation 2:
V_RNEG = g_m ⋅ V_OUT
(EQ. 2)
Where g_m is the gain of the transconductance amplifier.
A window voltage V_W is referenced with respect to the error
amplifier output voltage V_COMP, creating an envelope into
which the ripple voltage V_R is compared. The amplitude of
V_W is set by a resistor connected across the FSET and GND
pins. The V_R, V_COMP, and V_W signals feed into a window
comparator in which V_COMP is the lower threshold voltage
and V_W is the higher threshold voltage. Figure 6 shows
PWM pulses being generated as V_R traverses the V_W and
V_COMP thresholds. The PWM switching frequency is
proportional to the slew rates of the positive and negative
slopes of V_R; it is inversely proportional to the voltage
between V_W and V_COMP.
.
VIN
+
g_mV_IN
VO
+
g_mV_O
PWM FREQUENCY
CONTROL
+
V- _{W +}
V_R
+
-
C_{R TO} ^VCOMP +
PWM
CONTROL
FSET
R
PWM _Q
S
ISL6265
FIGURE 5. MODULATOR CIRCUITRY
RIPPLE CAPACITOR VOLTAGE C_R
WINDOW VOLTAGE V_W
ERROR AMPLIFIER VOLTAGE V_COMP
PWM
FIGURE 6. MODULATOR WAVEFORMS DURING LOAD
TRANSIENT
Initialization
Once sufficient bias is applied to the VCC pin, internal logic
checks the status of critical pins to determine the controller
operation profile prior to ENABLE. These pins include RTN1
which determines single vs two-phase operation and
OFS/VFIXEN for enabling/disabling the SVI interface and core
voltage droop. Depending on the configuration set by these
pins, the controller then checks the state of the SVC and SVD
pins to determine the soft-start target output voltage level.
Power-On Reset
The ISL6265 requires a +5V input supply tied to VCC and
PVCC to exceed a rising power-on reset (POR) threshold
before the controller has sufficient bias to guarantee proper
operation. Once this threshold is reached or exceeded, the
ISL6265 has enough bias to begin checking RTN1,
OFS/VFIXEN, ENABLE, and SVI inputs. Hysteresis between
the rising the falling thresholds assure the ISL6265 will not
inadvertently turn-off unless the bias voltage drops
substantially (see “Electrical Specifications” on page 8).
Core Configuration
The ISL6265 determines the core channel requirements of
the CPU based on the state of the RTN1 pin prior to
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FN6599.1
May 13, 2009