ISL6265 Datasheet, PDF (20/24 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

ISL6265
PWM outputs turn off both Core and Northbridge internal
drivers and PGOOD goes low.
General Application Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to design a single-phase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following section. In addition to this guide, Intersil provides
complete reference designs that include schematics, bills of
materials, and example board layouts.
Selecting the LC Output Filter
The output inductor and output capacitor bank form a
low-pass filter responsible for smoothing the pulsating
voltage at the phase node. The output filter also must
support the transient energy required by the load until the
controller can respond. Because it has a low bandwidth
compared to the switching frequency, the output filter limits
the system transient response. The output capacitors must
supply or sink load current while the current in the output
inductors increases or decreases to meet the demand.
The duty cycle of an ideal buck converter is a function of the
input and the output voltage. This relationship is written as
Equation 17:
D
=
-^V-----^O---
V_IN
(EQ. 17)
The output inductor peak-to-peak ripple current is written as
Equation 18:
I_P-P
=
V_-----O-----•_--(_---1_{-----–----}D_-----)
f_SW • L
(EQ. 18)
For this type of application, a typical step-down DC/DC
converter has an I_P-P of 20% to 40% of the maximum DC
output load current. The value of I_P-P is selected based upon
several criteria such as MOSFET switching loss, inductor
core loss, and the resistive loss of the inductor winding. The
DC copper loss of the inductor can be estimated by
Equation 19:
P_COPPER
=
I_L
O
A
2
D
•
D
C
R
(EQ. 19)
the capacitor. These two voltages are written as shown in
Equation 20:
ΔV_ESR = I_PP • ESR
(EQ. 20)
and Equation 21:
ΔV_C
=
-----------^I--^P----^P------------
8 • C_O • f_SW
(EQ. 21)
If the output of the converter has to support a load with high
pulsating current, several capacitors will need to be paralleled
to reduce the total ESR until the required V_P-P is achieved.
The inductance of the capacitor can cause a brief voltage dip
if the load transient has an extremely high slew rate. Capacitor
ESL can significantly impact output voltage ripple. Low
inductance capacitors should be considered. A capacitor
dissipates heat as a function of RMS current and frequency.
Be sure that I_P-P is shared by a sufficient quantity of paralleled
capacitors so that they operate below the maximum rated
RMS current at F_SW. Take into account that the rated value of
a capacitor can degrade as much as 50% as the DC voltage
across it increases.
Selection of the Input Capacitor
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capability must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs, which is related to duty cycle and the number of
active phases.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and capable of
supplying the RMS current required by the switching circuit.
Their voltage rating should be at least 1.25x greater than the
maximum input voltage, while a voltage rating of 1.5x is a
preferred rating. Figure 11 is a graph of the input RMS ripple
current, normalized relative to output load current, as a
function of duty cycle for a single-phase regulator that is
adjusted for converter efficiency.
Where I_LOAD is the converter output DC current.
The copper loss can be significant so attention must be
given to the DCR selection. Another factor to consider when
choosing the inductor is its saturation characteristics at
elevated temperature. A saturated inductor could cause
destruction of circuit components as well as nuisance OCP
faults.
A DC/DC buck regulator must have output capacitance C_O
into which ripple current I_P-P can flow. Current I_P-P develops
a corresponding ripple voltage V_P-P across C_O, which is the
sum of the voltage drop across the capacitor ESR and of the
voltage change stemming from charge moved in and out of
20
FN6599.1
May 13, 2009