ISL6265 Datasheet, PDF(15/24 Page) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

ISL6265 Datasheet, PDF (15/24 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

◁

ISL6265

SVC

SVD

6 5 4 32 10

SLAVE ADDRESS PHASE

(SEE TABLE 3)

SVID

7 654 3 210

DATA PHASE

FIGURE 8. SEND BYTE EXAMPLE

SVI Bus Protocol

The AMD processor bus protocol is compliant with SMBus

send byte protocol for VID transactions (see Figure 8).

During a send byte transaction, the processor sends the

start sequence followed by the slave address of the VR for

which the VID command applies. The address byte must be

configured according to Table 4. The processor then sends

the write bit. After the write bit, if the ISL6265 receives a

valid address byte, it sends the acknowledge bit. The

processor then sends the PSI-L bit and VID bits during the

data phase. The Serial VID 8-bit data field encoding is

outlined in Table 5. If ISL6265 receives a valid 8-bit code

during the data phase, it sends the acknowledge bit. Finally,

the processor sends the stop sequence. After the ISL6265

has detected the stop, it can then proceed with the VID-on-

the-fly transition.

TABLE 4. SVI SEND BYTE ADDRESS DESCRIPTION

BITS

DESCRIPTION

6:4 Always 110b

3 Reserved by AMD for future use

2 VDD1, if set then the following data byte contains the VID for

VDD1

1 VDD0, if set then the following data byte contains the VID for

VID0

0 VDDNB, if set then the following data byte contains the VID

for VIDNB

TABLE 5. SERIAL VID 8-BIT DATA FIELD ENCODING

BITS

DESCRIPTION

7 PSI_L:

= 0 means the processor is at an optimal load for the

regulator(s) to enter power-savings mode

= 1 means the processor is not at an optimal load for the

regulator(s) to enter power-saving mode

6:0 SVID[6:0] as defined in Table 3.

Operation

After the start-up sequence, the ISL6265 begins regulating

the core and Northbridge output voltages to the pre-PWROK

metal VID programmed. The controller monitors SVI

commands to determine when to enter power-savings mode,

implement dynamic VID changes, and shutdown individual

outputs.

The ISL6265 controls the no-load output voltage of core and

Northbridge output to an accuracy of Â±0.5% over-the-range

of 0.75V to 1.5V. A fully differential amplifier implements core

voltage sensing for precise voltage control at the

microprocessor die.

Switching Frequency

The R3 modulator scheme is a variable frequency PWM

architecture. The switching frequency increases during the

application of a load to improve transient performance. It

also varies slightly due to changes in input and output

voltage and output current. This variation is normally less

than 10% in continuous conduction mode.

CORE FREQUENCY SELECTION

A resistor connected between the VW and COMP pins of the

Core segment of the ISL6265 adjusts the switching window

and therefore adjusts the switching frequency. The RFSET

resistor that sets up the switching frequency of the converter

operating in CCM can be determined using Equation 3,

Designs for 300kHz switching frequency would result in a

(EQ. 3)

In discontinuous conduction mode (DCM) the ISL6265 runs

in period stretching mode.

NORTHBRIDGE FREQUENCY SELECTION

The Northbridge switching frequency to programmed by a

resistor connected from the FSET_NB pin to the GND pin.

The approximate PWM switching frequency is written as

shown in Equation 4:

FSW

-----------------1------------------

K â RFSETNB

(EQ. 4)

FN6599.1

May 13, 2009

▷