ISL6265 Datasheet, PDF (14/24 Pages) Intersil Corporation – Multi-Output Controller with Integrated MOSFET Drivers for AMD SVI Capable

ISL6265
SVI WIRE Protocol
The SVI wire protocol is based on the I²C bus concept. Two
wires (serial clock (SVC) and serial data (SVD)), carry
information between the AMD processor (master) and VR
controller (slave) on the bus. The master initiates and
terminates SVI transactions and drives the clock, SVC,
during a transaction. The AMD processor is always the
master and the voltage regulators are the slaves. The slave
receives the SVI transactions and acts accordingly. Mobile
SVI wire protocol timing is based on high-speed mode I²C.
See AMD Griffin (Family 11h) processor publications for
additional details.
TABLE 3. SERIAL VID CODES
SVID[6:0]
000_0000b
VOLTAGE (V)
1.5500
SVID[6:0]
010_0000b
VOLTAGE (V)
1.1500
SVID[6:0]
100_0000b
VOLTAGE (V)
0.7500
SVID[6:0]
110_0000b
VOLTAGE (V)
0.3500*
000_0001b
000_0010b
000_0011b
000_0100b
000_0101b
000_0110b
000_0111b
000_1000b
000_1001b
1.5375
1.5250
1.5125
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
010_0001b
010_0010b
010_0011b
010_0100b
010_0101b
010_0110b
010_0111b
010_1000b
010_1001b
1.1375
1.1250
1.1125
1.1000
1.0875
1.0750
1.0625
1.0500
1.0375
100_0001b
100_0010b
100_0011b
100_0100b
100_0101b
100_0110b
100_0111b
100_1000b
100_1001b
0.7375
0.7250
0.7125
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
110_0001b
110_0010b
110_0011b
110_0100b
110_0101b
110_0110b
110_0111b
110_1000b
110_1001b
0.3375*
0.3250*
0.3125*
0.3000*
0.2875*
0.2750*
0.2625*
0.2500*
0.2375*
000_1010b
000_1011b
1.4250
1.4125
010_1010b
010_1011b
1.0250
1.0125
100_1010b
100_1011b
0.6250
0.6125
110_1010b
110_1011b
0.2250*
0.2125*
000_1100b
000_1101b
000_1110b
000_1111b
001_0000b
001_0001b
001_0010b
001_0011b
001_0100b
1.4000
1.3875
1.3750
1.3625
1.3500
1.3375
1.3250
1.3125
1.3000
010_1100b
010_1101b
010_1110b
010_1111b
011_0000b
011_0001b
011_0010b
011_0011b
011_0100b
1.0000
0.9875
0.9750
0.9625
0.9500
0.9375
0.9250
0.9125
0.9000
100_1100b
100_1101b
100_1110b
100_1111b
101_0000b
101_0001b
101_0010b
101_0011b
101_0100b
0.6000
0.5875
0.5750
0.5625
0.5500
0.5375
0.5250
0.5125
0.5000
110_1100b
110_1101b
110_1110b
110_1111b
111_0000b
111_0001b
111_0010b
111_0011b
111_0100b
0.2000*
0.1875*
0.1750*
0.1625*
0.1500*
0.1375*
0.1250*
0.1125*
0.1000*
001_0101b
001_0110b
001_0111b
001_1000b
001_1001b
001_1010b
001_1011b
001_1100b
001_1101b
1.2875
1.2750
1.2625
1.2500
1.2375
1.2250
1.2125
1.2000
1.1875
011_0101b
011_0110b
011_0111b
011_1000b
011_1001b
011_1010b
011_1011b
011_1100b
011_1101b
0.8875
0.8750
0.8625
0.8500
0.8375
0.8250
0.8125
0.8000
0.7875
101_0101b
101_0110b
101_0111b
101_1000b
101_1001b
101_1010b
101_1011b
101_1100b
101_1101b
0.4875*
0.4750*
0.4625*
0.4500*
0.4375*
0.4250*
0.4125*
0.4000*
0.3875*
111_0101b
111_0110b
111_0111b
111_1000b
111_1001b
111_1010b
111_1011b
111_1100b
111_1101b
0.0875*
0.0750*
0.0625*
0.0500*
0.0375*
0.0250*
0.0125*
OFF
OFF
001_1110b
1.1750
011_1110b
0.7750
001_1111b
1.1625
011_1111b
0.7625
NOTE: *Indicates a VID not required for AMD Family 10h processors.
101_1110b
101_1111b
0.3750*
0.3625*
111_1110b
111_1111b
OFF
OFF
14
FN6599.1
May 13, 2009