ISL28022 Datasheet, PDF (23/28 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
0.20
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
SADC MODE
FIGURE 33. MEASUREMENT STABILITY vs SADC MODE
Fast Transients
An small isolation resistor placed between ISL28022 inputs and
the source is recommended. In hot swap or other fast transient
events, the amplitude of a signal can exceed the recommended
operating voltage of the part due to the line inductance. The
isolation resistor creates a low pass filter between the device and
the source. The value of the isolation resistor should not be too
large. A large value isolation resistor can effect the
measurement accuracy. The offset current for shunt input can be
as large as 10µA. The value of the isolation resistor combined
with the offset current creates an error offset voltage at the
shunt input. The input of the Bus channel is connected to the top
of a precision resistor divider. The accuracy of the resistor divider
determines the gain error of the Bus channel. The input
resistance of the Bus channel is 600kΩ. Placing an isolation
resistor of the 10Ω will change the gain error of the Bus channel
by 0.0016%.
External Clock
FUNCTION
GENERATOR
+
ECLK
-
VTH
VBUS
VINP
VINM
ISL28022 DPM
VCC
3.3V
GND
ADC
16-BIT
SCL
SDA
REG
A0
MAP
A1
FIGURE 34. SIMPLIFIED SCHEMATIC OF THE ISL28022
SYNCHRONIZED TO A PWM SOURCE
An externally controlled clock allows measurements to be
synchronized to an event that is time dependent. The event could
be application generated, such as timing a current measurement
to a charging capacitor in a switch regulator application or the
event could be environmental. A voltage or current measurement
may be suspectable to crosstalk from a controlled source.
Instead of filtering the environmental noise from the
measurement, another approach would be to synchronize the
measurement to the source. The variability and accuracy of the
measurement will improve.
The ISL28022 has the functionality to allow for synchronization
to an external clock. The speed of the external clock combined
with the choice of the internal chip frequency division value
determines the acquisition times of the ADC. The internal system
clock frequency is 500kHz. The internal system clock is also the
ADC sampling clock. The acquisition times scale linearly from
500kHz. For example, an external clock frequency of 1.0MHz
with a frequency divide setting of 2 results in acquisition times
that equals the internal oscillator frequency when enabled. The
internal clock frequency of the ISL28022 should not exceed
500kHz. The ADC modulator is optimized for frequencies of
500kHz and below. Operating internal clock frequencies above
500kHz result in measurement accuracy errors due to the
modulator not having enough time to settle.
Suppose an external clock frequency of 1.0MHz is applied with a
divide by 8 internal frequency setting, the system clock speed is
125kHz or 4x slower than internal system clock. The acquisition
times for this example will increase by 4. For a S(B)ADC setting
of 3, the ISL28022 will have an acquisition time of 2.032ms
instead of 508µs.
ECLK/INT
D
Q
D
Q
D
Q
FIGURE 35. SIMPLIFIED INTERNAL BLOCK CONNECTION OF THE
ECLK/INT PIN
The ECLK/INT pin connects to a buffer that drives a D-flip flop.
Figure 35 illustrates a simple schematic of the ECLK/INT pin
internal connection. The series of divide by 2 configured D-flip
flops are control by the CLKDIV bits from the Aux Control
Register. The buffer is a Schmitt triggered buffer. The bandwidth
of the buffer is 4MHz. Figure 36 shows the bandwidth of the
ECLK/INT pin.
5
CLKDIV = 5 (÷ 12)
4
SADC = 3
3
2
1
0
-1
1
10
EXTERNAL CLOCK FREQUENCY (MHz)
FIGURE 36. EXTERNAL CLOCK BANDWIDTH vs MEASUREMENT
ACCURANCY
23
FN8386.1
April 26, 2013