ISL28022 Datasheet, PDF (14/28 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
BRNG1
0
0
1
1
TABLE 3. BRNG BIT SETTINGS
BRNG0
USABLE FULL
SCALE RANGE
(V)
0
16
1
32
0
60
1
60
PG: PGA (Shunt Voltage Only)
Bits 11 and 12 of the configuration register determines the shunt
voltage measurement range. Table 4 shows the PGA bit
configurations versus the allowable full scale measurement
range. The shaded row is the power up default.
TABLE 4. PGA BIT SETTINGS
PG1
PG0
GAIN
0
0
1
0
1
÷2
1
0
÷4
1
1
÷8
RANGE
(mV)
±40
±80
±160
±300
BADC: Bus ADC Resolution/Averaging
Bits [10:7] of the configuration register sets the ADC resolution/
averaging when the ADC is configured in the V_BUS mode. The
ADC can be configured versus bit accuracy. The bit accuracy
selections range from 12 to 15-bits. The ADC is configurable
versus the number of averages. The selection ranges from 2 to
128 samples. Table 5 shows the breakdown of each BADC
setting. The shaded row is the default setting upon power up.
SADC: Shunt ADC Resolution/Averaging
Bits [10:7] of the configuration register sets the ADC resolution/
Averaging when the ADC is configured in the V_SHUNT mode. The
ADC can be configured versus bit accuracy. The bit accuracy
selections range from 12 to 15-bits. The ADC is configurable
versus number of averages. The selection ranges from 2 to 128
samples. Table 5 shows the break down of each SADC setting.
The shaded row is the default setting upon power-up.
MODE: Operating Mode
Bits [2:0] of the configuration register controls the state machine
within the chip. The state machine globally controls the overall
functionality of the chip. Table 6 shows the various states the
chip can be configured to, as well as the mode bit definitions to
achieve a desired state. The shaded row is the default setting upon
power-up.
ADC3
0
0
0
0
1
1
1
1
1
1
1
1
TABLE 5. ADC SETTINGS, APPLIES TO BOTH SADC AND BADC CONTROL
ADC2
ADC1
ADC0
MODE/SAMPLES
X
0
0
12-Bit
X
0
1
13-Bit
X
1
0
14-Bit
X
1
1
15-Bit
0
0
0
15-Bit
0
0
1
2
0
1
0
4
0
1
1
8
1
0
0
16
1
0
1
32
1
1
0
64
1
1
1
128
CONVERSION TIME
72µs
132µs
258µs
508µs
508µs
1.01ms
2.01ms
4.01ms
8.01ms
16.01ms
32.01ms
64.01ms
14
FN8386.1
April 26, 2013