ISL28022 Datasheet, PDF (21/28 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
SIGNALS
FROM THE
MASTER
S
T _{IDENTIFICATION}
A
BYTE WITH
R
R/W = 0
T
ADDRESS
BYTE
S
T _{IDENTIFICATION}
A
BYTE WITH
R
R/W = 1
T
S
A
T
C
O
K
P
SIGNAL AT
SDA
100nnnn0
A
SIGNALS FROM
C
THE SLAVE
K
100nnnn1
A
A
C
K
C
K
FIRST READ
DATA BYTE
SECOND READ
DATA BYTE
FIGURE 28. READ SEQUENCE (SLAVE ADDRESS SHOWN AS nnnn)
The last bit of the slave address byte defines a read or write
operation to be performed. When this R/W bit is a “1”, a read
operation is selected. A “0” selects a write operation (refer to
Figure 27).
After loading the entire slave address byte from the SDA bus, the
ISL28022 compares the loaded value to the internal slave address.
Upon a correct compare, the device outputs an acknowledge on the
SDA line.
valid memory location is 09h, reads of addresses higher than
that will not return useful data.
SLAVE ADDRESS
1
0
0
n
nn
n
R/W _BYTE
A7 A6 A5 A4 A3 A2 A1 A0 WORD ADDRESS
Following the slave byte is a one byte word address. The word
address is either supplied by the master device or obtained from an
internal counter. On power-up, the internal address counter is set to
address 00h, so a current address read starts at address 00h. When
required, as part of a random read, the master must supply the one
word address byte, as shown in Figure 28.
D15 D14 D13 D12 D11 D10 D9 D8 DATA BYTE 1
D7 D6 D5 D4 D3 D2 D1 D0 ^{DATA BYTE 2}
FIGURE 29. SLAVE ADDRESS, WORD ADDRESS, AND DATA BYTES
In a random read operation, the slave byte in the “dummy write”
portion must match the slave byte in the “read” section. For a
random read of the registers, the slave byte must be “100nnnnx” in
both places.
Write Operation
A write operation requires a START condition, followed by a valid
identification byte, a valid address byte, two data bytes, and a
STOP condition. The first data byte contains the LSB of the data,
the second contains the MSB. After each of the four bytes, the
ISL28022 responds with an ACK. At this time, the I²C interface
enters a standby state.
Broadcast Addressing
The DPM has a feature that allows the user to configure the settings
of all DPM chips at once. For example, a system has 16 DPM chips
connected to an I²C bus. A user can set the range or initiate a
data acquisition in one I²C data transaction by using a slave
address of 0111 111. The broadcast feature saves time in
configuring the DPM as well as measuring signal parameters in
time synchronization. The broadcast should not be used for DPM
read backs. This will cause all devices connected to the I²C bus
to talk to the master simultaneously.
I²C Clock Speed
Read Operation
A read operation consists of a three byte instruction, followed by
two data bytes (see Figure 28). The master initiates the operation
issuing the following sequence: A START, the identification byte
with the R/W bit set to “0”, an address byte, a second START, and a
second identification byte with the R/W bit set to “1”. After each of
the three bytes, the ISL28022 responds with an ACK. Then the
ISL28022 transmits two data bytes as long as the master
responds with an ACK during the SCL cycle following the eighth bit
of the first byte. The master terminates the read operation (issuing
no ACK then a STOP condition) following the last bit of the second
data byte (see Figure 28).
The data bytes are from the memory location indicated by an
internal pointer. This pointer’s initial value is determined by the
address byte in the read operation instruction, and increments by
one during transmission of each pair of data bytes. The highest
The ISL28022 supports high-speed digital transactions up to
3.4Mbs. To access the high speed I²C feature, a master byte
code of 0000 1nnn is attached to the beginning of a standard
frequency read/ write I²C protocol. The n in the master byte code
can either equal a 0 or a 1. The master byte code should be
clocked into the chip at frequencies equal or less than 400kHz.
The master code command configures the internal filters of the
ISL28022 to permit data bit frequencies greater than 400kHz.
Once the master code has been clocked into the device, the
protocol for a standard read/ write transaction is followed. The
frequency at which the standard protocol is clocked in at can be
as great as 3.4MHz. A stop bit at the end of a standard protocol
will terminate the high speed transaction mode. Appending
another standard protocol serial transaction to the data string
without a stop bit, will resume the high speed digital transaction
mode. Figure 30 illustrates the data sequence for the high speed
mode.
21
FN8386.1
April 26, 2013