ISL28022 Datasheet, PDF (19/28 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
I²C Serial Interface
The ISL28022 supports a bi-directional bus oriented protocol.
The protocol defines any device that sends data onto the bus as a
transmitter and the receiving device as the receiver. The device
controlling the transfer is the master and the device being
controlled is the slave. The master always initiates data transfers
and provides the clock for both transmit and receive operations.
Therefore, the ISL28022 operates as a slave device in all
applications.
The ISL28022 uses two bytes to transfer all reads and writes. All
communication over the I²C interface is conducted by sending
the MSByte of each byte of data first, followed by the LSByte.
Protocol Conventions
For normal operation, data states on the SDA line can change
only during SCL LOW periods. SDA state changes during SCL
HIGH are reserved for indicating START and STOP conditions (see
Figure 25). On power-up of the ISL28022, the SDA pin is in the
input mode.
All I²C interface operations must begin with a START condition,
which is a HIGH to LOW transition of SDA while SCL is HIGH. The
ISL28022 continuously monitors the SDA and SCL lines for the
START condition and does not respond to any command until this
condition is met (see Figure 25). A START condition is ignored
during the power-up sequence.
All I²C interface operations must be terminated by a STOP
condition, which is a LOW to HIGH transition of SDA while SCL is
HIGH (see Figure 25). A STOP condition at the end of a read
operation or at the end of a write operation to memory only places
the device in its standby mode.
SCL
SDA
START
DATA
DATA
DATA
STABLE CHANGE STABLE
FIGURE 25. VALID DATA CHANGES, START AND STOP CONDITIONS
STOP
SCL FROM
MASTER
1
8
9
SDA OUTPUT FROM
TRANSMITTER
HIGH IMPEDANCE
SDA OUTPUT FROM
RECEIVER
HIGH
START
FIGURE 26. ACKNOWLEDGE RESPONSE FROM RECEIVER
ACK
SIGNALS FROM THE
MASTER
SIGNAL AT SDA
SIGNALS FROM
THE ISL28022
S
WRITE
T
A ^{IDENTIFICATION}
R
BYTE
ADDRESS
BYTE
T
100nnnn0 0000
A
A
C
C
K
K
DATA
BYTE
A
C
K
DATA
BYTE
S
T
O
P
A
C
K
FIGURE 27. BYTE WRITE SEQUENCE (SLAVE ADDRESS INDICATED BY nnnn)
19
FN8386.1
April 26, 2013