ISL28022 Datasheet, PDF (16/28 Pages) Intersil Corporation – Precision Digital Power Monitor

ISL28022
.
TABLE 11. BUS VOLTAGE REGISTER, BRNG = 10 OR 11, FULL SCALE = 60V, 14 BITS WIDE
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
NAME Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1
WEIGHT 8192 4096 2048 1024 512 256 128 64 32 16
8
4
2
D2 D1 D0
Bit0 CNVR OVF
1
TABLE 12. BUS VOLTAGE REGISTER, BRNG = 01, FULL SCALE = 32V, 13 BITS WIDE
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3
NAME Bit12 Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
WEIGHT 4096 2048 1024 512 256 128 64 32 16
8
4
2
1
D2 D1 D0
CNVR OVF
TABLE 13. BUS VOLTAGE REGISTER, BRNG = 00, FULL SCALE = 16V, 12 BITS WIDE
Bit
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
NAME
Bit11 Bit10 Bit9 Bit8 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
WEIGHT
2048 1024 512 256 128 64 32 16
8
4
2
1
D2 D1 D0
CNVR OVF
TABLE 14. CALIBRATION REGISTER, 05h
Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME FS15 FS14 FS13 FS12 FS11 FS10 FS9 FS8 FS7 FS6 FS5 FS4 FS3 FS2 FS1 FS0
BUS VOLTAGE REGISTER 02H (READ-ONLY)
The Bus Voltage Register is where the DPM reports the measured
value of the V_bus. There are three scale ranges possible
depending on the BRNG setting controlled from the configuration
register(00H).
Tables 11 through 13 are the weight bits for each BRNG setting.
The binary value recorded in the Bus Voltage Register is
translated to a decimal value in the same way as the shunt
voltage register is converted to a decimal value.
⎡ ¹⁵
⎤
∑ ^{( ) Vbus}
⎢
⎢
Bit_n⋅Bit_Weight_n
⎥_⋅Vbus
⎥
LSB
⎣^{n = 0}
⎦
(EQ. 1)
Equation 1 is the mathematical equation for converting the
binary V_bus value to a decimal value. N is the bit number. The
LSB value for the V_bus measurement equals 4mV across all bus
range (BRNG) settings.
CNVR: Conversion Ready (Bit 1)
The Conversion Ready Bit indicates when the ADC has finished a
conversion and transferred the reading(s) to the appropriate
register(s). The CNVR is only operable when the DPM is set to one
of three trigger modes. The CNVR is at a high state when the
conversion is in progress. The CNVR transitions and remains at a
low state when the conversion is complete.
The CNVR bit is initialized or re-initialized in the following ways;
1. Writing to the configuration register.
2. Reading from Power Register
OVF: Math Overflow Flag (Bit 0)
The Math Overflow Flag (OVF) is a bit that is set to indicate the
current or power data being read from the DPM is over ranged
and meaningless.
CALIBRATION REGISTER 05H (READ/WRITE)
To accurately read the current and power measurements from
the chip, the calibration register needs to be programmed.
The calibration register value is calculated as follows:
1. Calculate the full scale current range that is desired. This is
calculated using Equation 2. R_shunt is the value of the shunt
resistor. Vshunt is the full scale setting that is desired. In most
cases, it is the PGA full scale range (300mV, 160mV, 80mV
and 40mV) that the DPM is programmed to.
Vshunt _FS
Current _{FS R shunt}
(EQ. 2)
2. From the current full scale range, the current LSB is
calculated using Equation 3. Current full scale is the outcome
from Equation 2. ADC_res is the resolution of shunt voltage
reading. The value is determined by the SADC setting in
configuration register. SADC setting equal to 3 and greater
will have a 15-bit resolution. The ADC_res value equals 2¹⁵ or
32768.
Current _FS
Current _{LSB ADC res}
(EQ. 3)
16
FN8386.1
April 26, 2013