X9520 Datasheet, PDF (2/33 Pages) Intersil Corporation – Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors

X9520
DETAILED DEVICE DESCRIPTION
The X9520 combines three Intersil Digitally Controlled
Potentiometer (DCP) devices, V1 / Vcc power-on reset
control, V1 / Vcc low voltage reset control, two supple-
mentary voltage monitors, and integrated EEPROM with
Block Lock™ protection, in one package. These func-
tions are suited to the control, support, and monitoring of
various system parameters in Fiber Channel / Gigabit
Ethernet fiber optic modules, such as in Gigabit Interface
Converter (GBIC) applications. The combination of the
X9520 fucntionality lowers system cost, increases reli-
ability, and reduces board space requirements using
Intersil’s unique XBGA™ packaging.
Two high resolution DCPs allow for the “set-and-forget”
adjustment of Laser Driver IC parameters such as Laser
Diode Bias and Modulation Currents. One lower resolu-
tion DCP may be used for setting sundry system param-
eters such as maximum laser output power (for eye
safety requirements).
Applying voltage to V_CC activates the Power-on Reset
circuit which allows the V1RO output to go HIGH, until
the supply the supply voltage stabilizes for a period of
time (selectable via software). The V1RO output then
goes LOW. The Low Voltage Reset circuitry allows the
V1RO output to go HIGH when V_CC falls below the mini-
mum V_CC trip point. V1RO remains HIGH until V_CC
returns to proper operating level. A Manual Reset (MR)
input allows the user to externally trigger the V1RO out-
put (HIGH).
Two supplementary Voltage Monitor circuits continuously
compare their inputs to individual trip voltages. If an input
voltage exceeds it’s associated trip level, a hardware
PIN CONFIGURATION
output (V3RO, V2RO) are allowed to go HIGH. If the
input voltage becomes lower than it’s associated trip
level, the corresponding output is driven LOW. A
corresponding binary representation of the two monitor
circuit outputs (V2RO and V3RO) are also stored in
latched, volatile (CONSTAT) register bits. The status of
these two monitor outputs can be read out via the 2-wire
serial port.
An application of the V1RO output may be to drive the
“ENABLE” input of a Laser Driver IC, with MR as a
“TX_DISABLE” input. V2RO and V3RO may be used to
monitor “TX_FAULT” and “RX_LOS” conditions respec-
tively.
Intersil’s unique circuits allow for all internal trip voltages
to be individually programmed with high accuracy. This
gives the designer great flexibility in changing system
parameters, either at the time of manufacture, or in the
field.
The memory portion of the device is a CMOS serial
EEPROM array with Intersil’s Block Lock™ protection.
This memory may be used to store fiber optic module
manufacturing data, serial numbers, or various other sys-
tem parameters. The EEPROM array is internally orga-
nized as x 8, and utilizes Intersil’s proprietary Direct
Write™ cells, providing a minimum endurance of
1,000,000 cycles and a minimum data retention of 100
years.
The device features a 2-Wire interface and software
protocol allowing operation on an I²C™ compatible
serial bus.
R_H2
R_W2
R_L2
V3
V3RO
MR
WP
SCL
SDA
V_SS
20 Pin TSSOP
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V1 / Vcc
V1RO
V2RO
V2
R_L0
R_W0
R_H0
R_H1
R_W1
R_L1
CSP
1
2
3
4
A ^{V2RO V1 / Vcc RW2 RL2}
V2 _V1RO R_{H2 V3}
B
C ^{RW0 RL0 V3RO WP}
R_H1 R_{H0 MR} SCL
D
V_SS R_W1 R_{L1 SDA}
E
Top View – Bumps Down
NOT TO SCALE
2
FN8206.0
March 8, 2005