X9520 Datasheet, PDF (14/33 Pages) Intersil Corporation – Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors

X9520
SCL
SDA
S 1 0 1 0 0 1 0 R/W A 1
T
C
A
K
R
T
SLAVE ADDRESS BYTE
1 11 1 1 1 1
ADDRESS BYTE
A CS7 CS6 CS5 CS4 CS3 CS2 CS1 CS0 A S
C
CT
K
KO
CONSTAT REGISTER DATA IN
P
Figure 18. CONSTAT Register Write Command Sequence
When the Block Lock bits of the CONSTAT register are
set to something other than BL1 = 0 and BL0 = 0, then
the “wiper position” of the DCPs cannot be changed - i.e.
DCP write operations cannot be conducted:
BL1 BL0
0
0
0
1
1
0
1
1
DCP Write Operation Permissible
YES (Default)
NO
NO
NO
The factory default setting for these bits are BL1 = 0,
BL0 = 0.
IMPORTANT NOTE: If the Write Protect (WP) pin of the
X9520 is active (HIGH), then all nonvolatile write opera-
tions to both the EEPROM memory and DCPs are inhib-
ited, irrespective of the Block Lock bit settings (See "WP:
Write Protection Pin").
POR1, POR0: Power-on Reset bits – (Nonvolatile)
Applying voltage to V_CC activates the Power-on Reset
circuit which holds V1RO output HIGH, until the supply
voltage stabilizes above the V_TRIP1 threshold for a
period of time, t_PURST (See Figure 30).
The Power-on Reset bits, POR1 and POR0 of the
CONSTAT register determine the t_PURST delay time of
the Power-on Reset circuitry (See "VOLTAGE MONI-
TORING FUNCTIONS"). These bits of the CONSTAT
register are nonvolatile, and therefore power-up to the
last written state.
The nominal Power-on Reset delay time can be selected
from the following table, by writing the appropriate bits to
the CONSTAT register:
POR1
0
0
1
1
POR0
0
1
0
1
Power-on Reset delay (t_PUV1RO)
50ms
100ms (Default)
200ms
300ms
The default for these bits are POR1 = 0, POR0 = 1.
V2OS, V3OS: Voltage Monitor Status Bits (Volatile)
Bits V2OS and V3OS of the CONSTAT register are
latched, volatile flag bits which indicate the status of the
Voltage Monitor reset output pins V2RO and V3RO.
At power-up the VxOS (x = 2,3) bits default to the value
“0”. These bits can be set to a “1” by writing the appropri-
ate value to the CONSTAT register. To provide consis-
tency between the VxRO and VxOS however, the status
of the VxOS bits can only be set to a “1” when the corre-
sponding VxRO output is HIGH.
Once the VxOS bits have been set to “1”, they will be
reset to “0” if:
—The device is powered down, then back up,
—The corresponding VxRO output becomes LOW.
14
FN8206.0
March 8, 2005