X9520 Datasheet, PDF (17/33 Pages) Intersil Corporation – Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors

X9520
V2 Monitoring
The X9520 asserts the V2RO output HIGH if the volt-
age V2 exceeds the corresponding V_TRIP2 threshold
(See Figure 21). The bit V2OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V2RO output may remain active HIGH with V_CC
down to 1V.
V3 Monitoring
The X9520 asserts the V3RO output HIGH if the volt-
age V3 exceeds the corresponding V_TRIP3 threshold
(See Figure 21). The bit V3OS in the CONSTAT regis-
ter is then set to a “0” (assuming that it has been set to
“1” after system initilization).
The V3RO output may remain active HIGH with V_CC
down to 1V.
V_TRIPX THRESHOLDS (X=1,2,3)
The X9520 is shipped with pre-programmed threshold
(V_TRIPx) voltages. In applications where the required
thresholds are different from the default values, or if a
higher precision / tolerance is required, the X9520 trip
points may be adjusted by the user, using the steps
detailed below.
Setting a V_TRIPx Voltage (x=1,2,3)
There are two procedures used to set the threshold
voltages (V_TRIPx), depending if the threshold voltage
to be stored is higher or lower than the present value.
For example, if the present V_TRIPx is 2.9 V and the
new V_TRIPx is 3.2 V, the new voltage can be stored
Vx
V_TRIPx
0V
VxRO
0V
V1 / Vcc
0 Volts
V_TRIP1
(x = 2,3)
Figure 21. Voltage Monitor Response
directly into the V_TRIPx cell. If however, the new set-
ting is to be lower than the present setting, then it is
necessary to “reset” the V_TRIPx voltage before setting
the new value.
Setting a Higher V_TRIPx Voltage (x=1,2,3)
To set a V_TRIPx threshold to a new voltage which is
higher than the present threshold, the user must apply
the desired V_TRIPx threshold voltage to the corre-
sponding input pin (V1 / Vcc, V2 or V3). Then, a pro-
gramming voltage (Vp) must be applied to the WP pin
before a START condition is set up on SDA. Next, issue
on the SDA pin the Slave Address A0h, followed by
the Byte Address 01h for V_TRIP1, 09h for V_TRIP2, and
0Dh for V_TRIP3, and a 00h Data Byte in order to pro-
gram V_TRIPx. The STOP bit following a valid write
operation initiates the programming sequence. Pin WP
must then be brought LOW to complete the operation
V1 / Vcc
V2, V3
WP
SCL
SDA
V_TRIPx
V_P
0 1 23 4 56 7
0 1 23 4 56 7
0 1 23 4 56 7
00h
†
A0h
S
T
A
R
01h^†
09h^†
0Dh^†
sets
sets
sets
V_TRIP1
V_TRIP2
V_TRIP3
Data Byte ^†
† _{All others Reserved.}
T
Figure 22. Setting V_TRIPx to a higher level (x=1,2,3).
17
FN8206.0
March 8, 2005