X9520 Datasheet, PDF (15/33 Pages) Intersil Corporation – Triple DCP, POR,2kbit EEPROM Memory, Dual Voltage Monitors

X9520
CONSTAT Register Write Operation
The CONSTAT register is accessed using the Slave
Address set to 1010010 (Refer to Figure 4.). Following
the Slave Address Byte, access to the CONSTAT regis-
ter requires an Address Byte which must be set to FFh.
Only one data byte is allowed to be written for each
CONSTAT register Write operation. The user must issue
a STOP, after sending this byte to the register, to initiate
the nonvolatile cycle that stores the BP1, BP0, POR1
and POR0 bits. The X9520 will not ACKNOWLEDGE
any data bytes written after the first byte is entered (Refer
to Figure 18.).
Prior to writing to the CONSTAT register, the WEL and
RWEL bits must be set using a two step process, with
the whole sequence requiring 3 steps
—Write a 02H to the CONSTAT Register to set the Write
Enable Latch (WEL). This is a volatile operation, so
there is no delay after the write. (Operation preceded
by a START and ended with a STOP).
—Write a 06H to the CONSTAT Register to set the Reg-
ister Write Enable Latch (RWEL) AND the WEL bit.
This is also a volatile cycle. The zeros in the data byte
are required. (Operation preceded by a START and
ended with a STOP).
—Write a one byte value to the CONSTAT Register that
has all the bits set to the desired state. The CONSTAT
register can be represented as qxyst01r in binary,
where xy are the Voltage Monitor Output Status
(V2OS and V3OS) bits, st are the Block Lock Protec-
tion (BL1 and BL0) bits, and qr are the Power-on Reset
delay time (t_PUV1RO) control bits (POR1 - POR0).
This operation is proceeded by a START and ended
with a STOP bit. Since this is a nonvolatile write cycle,
it will typically take 5ms to complete. The RWEL bit is
reset by this cycle and the sequence must be repeated
to change the nonvolatile bits again. If bit 2 is set to ‘1’
in this third step (qxys t11r) then the RWEL bit is set,
but the V2OS, V3OS, POR1, POR0, BL1 and BL0 bits
remain unchanged. Writing a second byte to the con-
trol register is not allowed. Doing so aborts the write
operation and the X9520 does not return an
ACKNOWLEDGE.
For example, a sequence of writes to the device CON-
STAT register consisting of [02H, 06H, 02H] will reset all
of the nonvolatile bits in the CONSTAT Register to “0”.
It should be noted that a write to any nonvolatile bit of
CONSTAT register will be ignored if the Write Protect
pin of the X9520 is active (HIGH) (See "WP: Write Pro-
tection Pin").
CONSTAT Register Read Operation
The contents of the CONSTAT Register can be read at
any time by performing a random read (See Figure 19).
Using the Slave Address Byte set to 10100101, and an
Address Byte of FFh. Only one byte is read by each reg-
ister read operation. The X9520 resets itself after the first
byte is read. The master should supply a STOP condition
to be consistent with the bus protocol.
After setting the WEL and / or the RWEL bit(s) to a “1”,
a CONSTAT register read operation may occur, without
interrupting a proceeding CONSTAT register write
operation.
Signals from
the Master
SDA Bus
Signals from
the Slave
S
t
a
r
Slave
Address
t
WRITE Operation
READ Operation
S
Address
t
a ^Slave
S
t
Byte
r Address
o
t
p
CS7 … CS0
10 1 0 0 1 0 0
10 1 0 0 1 01
A
A
C
C
K
K
A
C
K
Data
“Dummy” Write
Figure 19. CONSTAT Register Read Command Sequence
15
FN8206.0
March 8, 2005