ISL6146 Datasheet, PDF (2/23 Pages) Intersil Corporation – Low Voltage ORing FET Controller

ISL6146
Block Diagram
BIAS
Q-PUMP
FAULT DIAGNOSTIC
VIN
VOUT
1. V_IN - V_OUT > 570mV
VDS FORWARD
2. GATE - V_IN < 220mV
FLT
+ REGULATOR
3. TEMP > +150°C
GATE
4. V_BIAS < POR (ISL6146A/B)
20mV
REVERSE DETECTION
5. V_IN OR V_OUT < POR (ISL6146C)
6. V_IN < V_OUT
55mV ^COMPARATOR
+
UVLO
+
8mA
EN/EN
ENABLE
ENABLE _*
ADJ
4A
+ ^{HIGH SPEED}
COMPARATOR
* Connected to BIAS on ISL6146A/B
Connected to VOUT on ISL6146C
+
-
V_REF
ISL6146A/B
EN
OVP
+
+
-
V_REF
ISL6146C
Pin Configuration
ISL6146A, ISL6146B
ISL6146
(8 LD MSOP/DFN)
TOP VIEW
GATE ₁
VIN ₂
BIAS ₃
EN ISL6146A ₄
EN ISL6146B
8 VOUT
7 _ADJ
6 FAULT
5 GND
GATE 1
VIN ₂
UVLO ³
OVP ⁴
EPAD on DFN only, connect to GND
ISL6146C
8 VOUT
7 ADJ
6 FAULT
5 GND
Pin Descriptions
MSOP/
DFN SYMBOL
DESCRIPTION
1
GATE Gate Drive output to the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically
<1ms. Allows active control of external N-Channel FET gate to perform ORing function.
The GATE drive is between V_IN + 7V at V_IN = 3.3V and V_IN +12V at V_IN = 18V.
2
VIN Connected to the sourcing supply side (ORing MOSFET Source), this pin serves as the sense pin to determine the OR’d supply
voltage. The ORing MOSFET will be turned off when V_IN becomes lower than V_OUT by a value more than the externally set
threshold or the defaulted internal threshold. Range: 0 to 24V
3
ISL6146A
ISL6146B
BIAS
Primary bias pin. Connected to an independent voltage supply greater than or equal to 3V and greater than V_IN.
Range: 3.0 to 24V
3
ISL6146C
UVLO
Programmable UVLO protection to prevent premature turn-on prior to VIN being adequately biased. Range: 0 to 24V
4
EN Active high enable input to turn on the FET. Internally pulled low to GND through 2MΩ
ISL6146A
Range: 0 to 24V
4
EN Active low enable input to turn on the FET. Internally pulled high to BIAS through 2MΩ. Range: 0 to 24V
ISL6146B
2
FN7667.0
December 16, 2011