ISL6146 Datasheet, PDF (15/23 Pages) Intersil Corporation – Low Voltage ORing FET Controller

ISL6146
Functional Description
Functional Overview
In a redundant power distribution system, similar potential and
parallel power supplies each contribute to the load current
through various active and passive current sharing schemes.
Typically ORing power diodes are used to protect against reverse
current flow in the event that one of the power supplies falls
below the common bus voltage or develops a catastrophic
failure. However, using a discrete ORing diode solution has some
significant drawbacks. The primary downside is the increased
power dissipation loss in the ORing diodes as system power
requirements increase. At the lowest voltages where the ISL6146
is designed for use, the voltage distribution losses across an
ORing diode can be a significant percentage, in some cases
approaching 70%. Another disadvantage when using an ORing
diode, is failure to detect a shorted or opened current path which
jeopardizes system power availability and reliability. An open
diode may reduce the system to a single point of failure while a
shorted diode eliminates the system’s power protection.
Using an active ORing FET controller such as the ISL6146 helps
with these potential issues. The use of a low on-resistance FET as
the ORing component allows for a more efficient system design
as the voltage across the FET is much lower than that across a
forward biased diode. Additionally, the ISL6146 has a dedicated
fault (FAULT) output pin that will indicate when there is a
conditional or FET fault short providing the diagnostic capability a
diode is unable to.
The ISL6146 is designed to OR together voltages as low as 1V
when supplied with a separate bias supply of 3V or greater.
Otherwise, the ISL6146 is designed to be biased from and OR
voltages across the 3V to 20V nominal supply range.
In a single FET configuration as voltage is first applied to a VIN
pin, the FET body diode conducts providing all the ISL6146s
connected on a common bus circuit, bias via the VOUT pins. As
individual power supply voltages ramp up in excess of the rising
POR threshold, the ISL6146’s internal charge pump activates to
provide a floating gate drive voltage for the external N-channel
ORing MOSFET, thus turning the FETs on once V_IN > V_OUT. The
ISL6146 continuously monitors the drain and source of the
ORing FET and provides a reverse voltage (N-channel MOSFET
V_OUT - V_IN) detection threshold (VR) that, when exceeded,
indicates a reverse current condition. Once this threshold is
exceeded, the ISL6146 will turn-off the ORing FET by pulling
down the GATE pin to GND. The ISL6146 also provides high
speed V_OUT > V_IN transient protection as in the case of a
catastrophic VIN failure. The ISL6146 additionally provides for
adjustment of the V_IN - V_OUT reverse voltage Vth(VR Vth) via the
ADJ pin of the ISL6146 with an external resistor to GND. This
allows adjusting the V_IN - V_OUT voltage threshold level to
compensate for normal system voltage fluctuations, thus
eliminating unnecessary reaction by the ISL6146.
The total V_IN - V_OUT VR Vth is the sum of both the internal offset
and the external programmed VR Vth.
In the event of a V_OUT > V_IN condition, the ISL6146 responds
either with a high or low current pull-down on the GATE pin
depending on whether the High Speed comparator (HSCOMP)
has been activated or not. The HSCOMP determines if the VR
occurred within 1μs by continuously sampling the FET VDS and if
so, the high pull-down current is used to turn off the ORing FET. In
the event of a falling VIN transition in <1μs, (i.e., a catastrophic
failure of the power source) the HSCOMP protects the common
bus from the individual faulted power supply short by turning off
the shorted supply’s ORing MOSFET in less than 300ns, ensuring
the integrity of the common bus voltage from reverse current to
the damaged supply.
Once the correct V_IN > V_OUT relationship is established again, the
ISL6146 will again turn on the FET.
The FAULT pin is an open drain, active low output indicating that
a fault or specific condition has occurred, these include:
• GATE is OFF (GATE < V_IN+0.2V). Lack of conduction, not a fault,
just not on.
• Faults resulting in V_IN - V_OUT > 0.57V when ON.
• An open FET resulting in body diode conduction
• Excessive current through FET
• FET Faults monitored and reported include
- G-D, gate unable to drive to Q-pump voltage
- G-S, gate unable to drive to Q-pump voltage
- D-S shorts, when GATE is OFF VDS < 2V
- V_IN < POR
- Missing V_IN
- V_IN shorted to GND
On the ISL6146C version, a conditional fault will also be
signalled if the V_IN is not within the programmed UVLO and OVP
levels.
The ISL6146 has an on-chip over-temperature fault threshold of
~+140°C with a 20°C hysteresis. Although the ISL6146 itself
produces little heat, it senses the environment in which it is,
likely including a close by FET.
The ISL6146A and ISL6146B are functional variants with an
enabling input of either polarity. This feature is used when the
need to interrupt the current path via signaling is necessary. This
is accomplished by implementing two FETs in series so that there
is a body diode positioned to block current in either direction.
This functionality is considered an additional enhancement to
the ORing diode it replaces.
The ISL6146C employs the use of a programmable Undervoltage
Lock Out (UVLO) and a programmable Overvoltage Protection
(OVP) input. This allows the GATE to only turn-on when the
monitored voltage is between the programmed lower and upper
levels. This application would use the back-to-back FET
configuration. In the event the current path does not need to be
interrupted then the EN, UVLO and OVP inputs can all be
overridden.
15
FN7667.0
December 16, 2011