ISL6146 Datasheet, PDF (17/23 Pages) Intersil Corporation – Low Voltage ORing FET Controller

ISL6146
The Figure 1 circuit shown on page 1 is the basic circuit used for
ORing voltages >3V to 20V.
The ISL6146A application shown in Figure 43 is the configuration
for ORing very low voltages of 1V to 3V. Additionally, this
application shows the utilization of the ADJ input with a single
resistor tied to GND. This provides the user a programmable level
of V_OUT > V_IN before the High Speed (HS) Comparator is activated
and the GATE output is pulled down to allow for normal voltage
fluctuations in the system.
Notice that in both of these circuits, the EN or EN inputs are
defaulted to enabled and have no current path on/off control.
Failure to do so correctly will result in only body diode conduction
and a resulting fault indication.
The V_IN and V_OUT to FET and GND to ADJ connections are drawn
to emphasize the Kelvin connection necessary to correctly
monitor the voltage across the FET, and for the VR Vth monitor to
eliminate any stray resistance effects.
+
VOLTAGE
DC - DC
3V-20V
-
Q1 Q2
VIN GATE VOUT
UVLO
ADJ
ISL6146C
OVP
FLT
GND
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
+
Q3 Q4
C
+
O
M
M
O
N
VIN GATE VOUT
P
VOLTAGE
DC - DC
UVLO
ADJ
O
W
3V-20V
ISL6146C
E
R
OVP
FLT
B
U
GND
S
-
When using the back-to-back FET configuration, the user must
chose FETs to ensure (2r_DS(ON) + PCB IR) I_LOAD < 0.5V to avoid
tripping the V_IN - V_OUT > 0.5V when ON fault.
DISTRIBUTED
VOLTAGE
>3V
+
VERY LOW
VOLTAGE
DC - DC
(1V-BIAS)
-
+
VERY LOW
VOLTAGE
DC - DC
(1V-BIAS)
-
Q1 Q2
VIN GATE VOUT
BIAS
ADJ
ISL6146A/B
FLT
GND EN/EN
+
C
O
M
M
O
N
P
O
W
E
R
ENABLED _B
WHEN
U
SIGNALED S
Q3 Q4
VIN GATE VOUT
BIAS
ADJ
ISL6146A/B
FLT
GND EN/EN
+
C
O
M
M
O
N
P
O
W
E
R
B
ENABLED U
WHEN
S
SIGNALED
FIGURE 45. CONTROLLED ON/OFF APPLICATION DIAGRAM
The application diagram in Figure 45 shows the ISL6146A or
ISL6146B utilizing the EN or EN pin as a signalled input to open
or close the conduction path from power supply to load. This
feature can be implemented on ORing 1V to 20V but is shown for
ORing <3V.
The enable input signaling can be simultaneous across the N+1
number of ISL6146s used.
Although not needed for thermal relief, connect the DFN EPAD
to GND.
FIGURE 44. TYPICAL ISL6146C APPLICATION DIAGRAM
The ISL6146C application shown in Figure 44 is limited to the 3V
to 20V V_IN range and must implement the back-to-back FET
configuration to utilize the UVLO and OVP inputs and capabilities.
As the V_IN voltage rises above the minimum programmed
voltage, the related ORing FETs will turn on and stay on until
either the minimum voltage requirement is no longer met or the
V_IN voltage exceeds its programmed maximum. The minimum
and maximum programmed voltage levels are done with the
resistor divider on the UVLO and OVP pins. These levels should be
programmed to take into account conduction path losses to the
load in addition to the IC operational constraints.
17
FN7667.0
December 16, 2011