ISL6146 Datasheet, PDF (16/23 Pages) Intersil Corporation – Low Voltage ORing FET Controller

ISL6146
Applications Information
Power-Up Considerations
BIAS AND V_IN CONSTRAINTS
Upon power-up when the V_IN supply is separate from the BIAS
supply, the BIAS voltage must be greater or equal to the V_IN
voltage at all times.
When using a single supply for both the ISL6146 bias and the
ORing supply, the V_IN and BIAS pins can be configured with a low
value resistor between the two pins to provide some isolation and
decoupling to support the chip bias even as the OR’d supply
experiences voltage droops and surges. Although not necessary
to do so, it is a best design practice for particularly noisy
environments.
FET TO IC LAYOUT RECOMMENDATIONS
Connections from the FET(s) to the ISL6146 VIN and VOUT pins
must be kelvin in nature, as close to the FET drain and source
PCB pads as possible to eliminate any trace resistance errors
that can occur with high currents. This connection placement is
most critical to providing the most accurate voltage sensing
particularly when the back-to-back FET configuration is used.
Likewise, connections from OVP, UVLO and ADJ are also critical to
optimize accuracy.
ADJUSTING THE HS COMPARATOR REVERSE VOLTAGE
THRESHOLD
The ISL6146 allows adjustment of the HS Comparator reverse
voltage detection threshold (VR Vth), the difference in V_OUT - V_IN.
There are two valid ADJ pin configurations:
1. ADJ connected to VOUT: This makes the HS comparator
threshold equal to the intrinsic error in the HS comparator
input. This is the default condition and the most likely used
configuration.
2. A single resistor is connected from ADJ pin to ground:
Making the HS comparator threshold = V_OUT - 4k/R_ADJ.
Where 4k = 0.4(V_ADJ)*10kΩ
So, for a 100kΩ R_EXT, HS Comparator threshold = 40mV and for
a 5kΩ R_EXT HS comparator threshold = ~ 800mV.
The recommended resistor range is 5kΩ to 100kΩ for this
voltage adjustment.
At power-up, the HS comparator threshold is default set to the
internal device error first, and then released to the user
programmed threshold after the related circuits are ready. It
takes ~20μs for the circuit to switch from the default setting to
the user programmed threshold after a POR startup.
The current out of the ADJ pin with a resistor to GND is equal to
0.4V of the ADJ resistor.
BACK-TO-BACK FET CONFIGURATION
When using the back-to-back FET configuration, the FET choice
must be such that the voltage across both FETs at full current
loading be less than the minimum forward voltage fault
threshold of 400mV to avoid unintended fault notification.
In this configuration, it may be tempting to use the enable inputs
to force a path by switching between the two as opposed to
having both paths on and having the higher voltage source
provide current. The problem with that is the timing of the FETs
on and off so that excessive V_OUT voltage droop is not introduced
if the turn-off happens faster or before the turn-on momentarily
leaves inadequate power to the load.
Typical Applications Circuits
There are four basic configurations that the ISL6146 can be
used in:
1. For voltages >3V where the BIAS and V_IN are common
2. For a very low ORing voltage, <3V operation, BIAS >3V
3. For a voltage window compliant operation and
4. For a signaled operation where the current path is controlled
by an input signal or minimum voltage condition.
Each of these configurations can be tailored for the High Speed
Comparator (HS COMP) reverse threshold via the ADJ input being
connected either to VOUT or to GND via a resistor as explained
previously. Additionally, the voltage window is adjustable for both
a minimum and maximum operating voltage via the UVLO and
OVP inputs and a resistor divider also explained earlier. Also
soft-start and turn-on and turn-off characteristics can be tailored
to suit.
The three evaluation platforms provided demonstrate the four
basic configurations and provide for the additional tailoring of
the various performance characteristics.
BIAS
VOLTAGE
>3V
Q1
+
VERY LOW
VOLTAGE
DC - DC
(1V-3V)
-
VIN GATE
BIAS
VOUT
ADJ
EN
ISL6146A
FLT
GND
Q2
+
VERY LOW
VOLTAGE
DC - DC
(1V-3V)
-
VIN GATE VOUT
BIAS
ADJ
ISL6146A
FLT
EN
GND
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
+
C
O
M
M
O
N
P
O
W
E
R
B
U
S
FIGURE 43. LOW VOLTAGE APPLICATION DIAGRAM
16
FN7667.0
December 16, 2011