ISL6540_06 Datasheet, PDF (19/20 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540
0.60
0.50
0.40
0.5Io
0.30
0.20
0.10
0.25Io
∆I=0Io
0.00
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
DUTY CYCLE (D)
FIGURE 12. INPUT-CAPACITOR CURRENT MULTIPLIER FOR
SINGLE-PHASE BUCK CONVERTER
input voltage and a voltage rating of 1.5 times is a
conservative guideline. The RMS current rating requirement
for the input capacitor of a buck regulator is approximately
below.
I_{IN, RMS} =
I_O2
(
D
–
D²
)
+
∆_----I_--²_-
12
D
D = --^V----^O----
VIN
OR
I_{IN, RMS} = K_ICM • I_O
For a through hole design, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-
GX or equivalent) may be needed. For surface mount
designs, solid tantalum capacitors can be used, but caution
must be exercised with regard to the capacitor surge current
rating. These capacitors must be capable of handling the
surge-current at power-up. The TPS series available from
AVX, and the 593D series from Sprague are both surge
current tested.
MOSFET Selection/Considerations
The ISL6540 requires 2 N-Channel power MOSFETs. These
should be selected based upon r_DS(ON), gate supply
requirements, and thermal management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor (see the equations below). The
upper MOSFET exhibits turn-on and turn-off switching
losses as well as the reverse recover loss, while the
synchronous rectifier exhibits body-diode conduction losses
during the leading and trailing edge dead times.
P_LOWER
=


I_O2
+
-^∆₁---^I-₂-²- _
•
r_{---D----S----(--O-----N----)--,-L--}
N_L
•
(
1
–
D
)
+
P_D
E
A
D
P_DEAD =


I_O
+
1^-∆---2^{-I-}
•
V_DT
•
t_DT
+


I_O
–
1^-∆---2^{-I-}
•
V_DL
•
t_DL
• F_S
P_UPPER
=
^IO2 ^{+ -∆}₁^---I-₂^-2-
•
r_{---D----S----(--O-----N----)--,-U--}
N_U
•
D
+
P_SW
+
P_Qrr
P_SW =
 ^IO
+
1^-∆---2^{-I-}
•
t_OFF
+


I_O
–
1^-∆---2^{-I-}
•
t_ON
• VIN • F_S
P_Qrr = Q_rr • VIN • F_S
where D is the duty cycle = V_O / VIN; Q_rr is the reverse
recover charge; t_DLand t_DT are leading and trailing edge
dead time, and t_ON & t_OFF are the switching intervals.
These equations do not include the gate-charge losses that
are proportional to the total gate charge and the switching
frequency and partially dissipated by the internal gate
resistance of the MOSFETs. Ensure that both MOSFETs are
within their maximum junction temperature at high ambient
temperature by calculating the temperature rise according to
package thermal-resistance specifications. A separate
heatsink may be necessary depending upon MOSFET
power, package type, ambient temperature and air flow.
ISL6540 DC/DC Converter Application Circuit
Detailed information on the application circuit, including a
complete Bill-of-Materials and circuit board description, can
be found in application note AN1204. See Intersil’s home
page on the web: http://www.intersil.com.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
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19
FN9214.0
March 9, 2006