ISL6540_06 Datasheet, PDF (14/20 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540
voltage at OFS+ to be increased. In both modes the voltage
difference between OFS+ and OFS- is then sensed with an
instrumentation amplifier and is converted to the desired
margining voltage by a 5:1 ratio. The maximum designed
margining range of the ISL6540 is ±200mV, this sets the
MINIMUM value of R_OFS+ or R_OFS- at approximately 5.9K
for an R_MARG of 10K for a MAXIMUM of 1V across R_MARG.
The OFS pins are completely independent and can be set to
different margining levels. The maximum usable reference
voltage for the ISL6540 is VCC-1.8V, and should not be
exceeded when using the margining functionality, i.e,
V_{REF_MARG} < VCC - 1.8V.
V _{M A R G _UP}
=
-^V----^R----^E----^F- • ^R-----^M-----^A----^R----^G--
5
R_OFS+
V _{M A R G _DOWN}
=
V_{-----R----E----F-}
5
•
-^R----^M-----^A----^R----^G--
R_OFS-
An alternative calculation provides for a desired percentage
change in the output voltage when using the internal 0.591V
reference:
V _{P C T _UP}
=
20 • ^R-----^M-----^A----^R----^G--
R_OFS+
V _{p c t _DOWN}
=
20
•
R_{-----M-----A----R----G--}
R_OFS-
When not used in a design OFS+, OFS-, and MARCTRL
should be left floating. To prevent damage to the part, OFS+
and OFS- should not be tied to VCC or PVCC.
Reference Output Buffer
The internal buffer’s output tracks the unmargined system
reference. It has a 19mA drive capability, with maximum and
minimum output voltage capabilities of VCC and GND
respectively. Its capacitive loading can range from 1µF to
above 17.6µF, which is designed for 1 to 8 DIMM systems in
DDR (Dual Data Rate) applications. 1µF of capacitance
should always be present on REFOUT. It is not designed to
drive a resistive load and any such load added to the system
should be kept above 300kΩ total impedance.
Reference Input
The REFIN pin allows the user to bypass the internal 0.591V
reference with an external reference. Asynchronously if
REFIN is NOT within ~800mV of VCC, the external
reference pin is used as the control reference instead of the
internal 0.591V reference. The minimum usable REFIN
voltage is ~60mV while the maximum is VCC - 1.8V -
V_MARG (if present). The limitation is set by the error
amplifier's maximum common mode input range of VCC -
1.8V for the industrial temperature ranges.
REFERENCE
V_REF=0.591V
VCC
ISL6540
STATE
MACHINE
REFIN
800mV
REFOUT
MARGINING ^VREF_MARG
BLOCK
OTA
FIGURE 5. SIMPLIFIED REFERENCE BUFFER
Internal Reference and System Accuracy
The internal reference is trimmed to 0.591V. The total DC
system accuracy of the system is within 0.85% over
commercial temperature range, and 1.25% over industrial
temperature range. System accuracy includes error amplifier
offset, OTA error, and bandgap error. Differential remote
sense offset error is not included. As a result, if the
differential remote sense is used, then an extra 3mV of offset
error enters the system. The use of REFIN may add up to
1.8mV of additional offset error.
Differential Remote Sense Buffer
The differential remote sense buffer is essentially an
instrumentation amplifier with unity gain. The offset is
trimmed to 3mV for high system accuracy. As with any
instrumentation amplifier typically 6µA are sourced from the
VSEN- pin. The output of the remote sense buffer is
connected directly to the internal OV/UV comparator. As a
result, a resistor divider should be placed on the input of the
buffer for proper regulation, as shown in Figure 6. The
VMON pin should be connected to the FB pin by a standard
feed-back network. A small capacitor, C_SEN in Figure 6, can
be added to filter out noise, typically C_SEN is chosen so the
corresponding time constant does not reduce the overall
phase margin of the design, typically this is 2x to 10x
switching frequency of the regulator.
As some applications will not use the differential remote
sense, the output of the remote sense buffer can be disabled
(high impedance) by pulling VSEN- within 800mV of VCC.
As the VMON pin is connected internally to the
OV/UV/PGOOD comparator, an external resistor divider
must then be connected to VMON to provide correct voltage
information for the OV/UV comparator. An RC filter should
be used if VMON is to be connected directly to FB instead of
to VOUT through a separate resistor divider network. This
filter prevents noise injection from disturbing the
OV/UV/PGOOD comparators on VMON. VMON may also be
connected to the SS pin, which completely bypasses the
OV/UV/PGOOD functionality.
14
FN9214.0
March 9, 2006