ISL6540_06 Datasheet, PDF (11/20 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540
Functional Description
Initialization
The ISL6540 automatically initializes upon receipt of power
without requiring any special sequencing of the input
supplies. The Power-On Reset (POR) function continually
monitors the input supply voltages (PVCC,VFF, VCC) and
the voltage at the EN pin. Assuming the EN pin is pulled to
above ~0.49V, the POR function initiates soft-start operation
after all input supplies exceed their POR thresholds.
HIGH = ABOVE POR; LOW = BELOW POR
VCC POR
VFF POR
PVCC POR
EN POR
AND
SOFT-START
FIGURE 1. SOFT-START INITIALIZATION LOGIC
With all input supplies above their POR thresholds, driving
the EN pin above 0.49 V initiates a soft-start cycle. In
addition to normal TTL logic, the enable pin can be used as
a voltage monitor with programmable hysteresis through the
use of the internal 10µA sink current and an external resistor
divider. This feature is especially designed for applications
that have input rails greater than a 3.3V and require a
specific input rail POR and Hysteresis levels for better
undervoltage protection. Consider for a 12V application
choosing R_UP = 100kΩ and R_DOWN = 5.76kΩ there by
setting the rising threshold (V_{EN_RTH}) to 10V and the falling
threshold (V_{EN_FTH}) to 9V, for 1V of hysteresis (V_{EN_HYS}).
Care should be taken to prevent the voltage at the EN pin
from exceeding VCC when using the programmable UVLO
functionality.
VIN
R_UP
R_DOWN
V_REF
Sys_Enable
I_{EN_HYS}=10µA
Soft-start
The POR function activates the internal 38µA OTA which
begins charging the external capacitor (C_SS) on the SS pin to a
target voltage of VCC. The ISL6540’s soft-start logic continues
to charge the SS pin until the voltage on COMP exceeds the
bottom of the oscillator ramp, at which point, the driver outputs
are enabled, with the low side MOSFET first being held low for
200ns to provide for charging of the bootstrap capacitor. Once
the driver outputs are enabled, the OTA’s target voltage is then
changed to the margined (if margining is being used) reference
voltage (V_{REF_MARG}), and the SS pin is ramped up or down
accordingly. This method reduces startup surge currents due to
a pre-charged output by inhibiting regulator switching until the
control loop enters its linear region. By ramping the positive
input of the error amplifier to VCC and then to V_{REF_MARG}, it is
even possible to mitigate surge currents from outputs that are
pre-charged above the set output voltage. As the SS pin
connects directly to the non-inverting input of the Error
Amplifier, noise on this pin should be kept to a minimum
through careful routing and part placement. To prevent noise
injection into the error amplifier the SS capacitor should be
located within 150mils of the SS and GND pins. Soft-start is
declared done when the drivers have been enabled and the SS
pin is within ±3mV of V_{REF_MARG}.
Power Good
The power good comparator references the voltage on the
soft-start pin to prevent accidental tripping during margining.
The trip points are shown on Figure 3. Additionally, power
good will not be asserted until after the completion of the soft-
start cycle. A 0.1µF capacitor at the PG_DLY pin will add an
additional ~5ms delay to the assertion of power good.
PG_DLY does not delay the deassertion of power good.
VMON
+15%
+9%
V_{REF_MARG}
-9%
-15%
R_UP
=
V_{-----E----N----_---H----Y---S--}
I _{E N _HYS}
R_DOWN = _V-----_E--^R--_N---^U-_{_}---_FP---_T--^•-_H---^V--–--^E---_V-^N---_E--^_--_N-^R---^E_---_R-^F---_E----_F-
V_{EN_FTH} = V_{EN_RTH} – V_{EN_HYS}
FIGURE 2. ENABLE POR CIRCUIT
GOOD
GOOD
UV
OV
UV
FIGURE 3. UNDERVOLTAGE-OVERVOLTAGE WINDOW
T _{P G _DLY}
=
C_P
G
_DLY
⋅
--¹---^.--⁵---^V----
30 µ A
Under and Overvoltage Protection
The Undervoltage (UV) and Overvoltage (OV) protection
circuitry compares the voltage on the VMON pin with the
11
FN9214.0
March 9, 2006