ISL6540_06 Datasheet, PDF (17/20 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540
R₂
=
---^V-----^O----^S----^C-----^â‹---^R-----¹----^â‹---^F----⁰-----
d_MAX ⋅ V_IN ⋅ F_LC
A small capacitor, C_SEN in Figure 10, can be added to filter
out noise, typically C_SEN is chosen so the corresponding
time constant does not reduce the overall phase margin
of the design, typically this is 2x to 10x switching
frequency of the regulator. As the ISL6540 supports
100% duty cycle, d_MAX equals 1. The ISL6540 also uses
feedforward compensation, as such V_OSC is equal to
0.16 multiplied by the voltage at the VFF pin. When tieing
VFF to V_IN the above equation simplifies to:
R₂
=
0_----._--1_---6_-----⋅_---R_----1-----⋅_---F_----0-
F_LC
2. Calculate C₁ such that F_Z1 is placed at a fraction of the F_LC,
at 0.1 to 0.75 of F_LC (to adjust, change the 0.5 factor to
desired number). The higher the quality factor of the output
filter and/or the higher the ratio F_CE/F_LC, the lower the F_Z1
frequency (to maximize phase boost at F_LC).
C₁
=
-----------------------¹-----------------------
2π ⋅ R₂ ⋅ 0.5 ⋅ F_LC
3. Calculate C₂ such that F_P1 is placed at F_CE.
C₂ = -₂---_π-----_â‹---_R-----₂----_â‹---_C-^C----₁-¹---_â‹---_F----_C----_E-----–-----₁-
4. Calculate R₃ such that F_Z2 is placed at F_LC. Calculate C₃
such that F_P2 is placed below F_SW (typically, 0.5 to 1.0
times F_SW). F_SW represents the regulator’s switching
frequency. Change the numerical factor to reflect desired
placement of this pole. Placement of F_P2 lower in frequency
helps reduce the gain of the compensation network at high
frequency, in turn reducing the HF ripple component at the
COMP pin and minimizing resultant duty cycle jitter.
R₃
=
--------^R-----¹--------
F_{----S----W---- – 1}
F_LC
C₃
=
-----------------------¹-------------------------
2π ⋅ R₃ ⋅ 0.7 ⋅ F_SW
It is recommended that a mathematical model is used to plot
the loop response. Check the loop gain against the error
amplifier’s open-loop gain. Verify phase margin results and
adjust as necessary. The following equations describe the
frequency response of the modulator (G_MOD), feedback
compensation (G_FB) and closed-loop response (G_CL):
G_MOD(f)
=
-^d---^M-----^A----^X-----^â‹---^V----^I--^N--
V_OSC
⋅
-------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---^E-----^S----^R------^â‹---^C----------------------------------
1 + s(f) ⋅ (ESR + DCR) ⋅ C + s²(f) ⋅ L ⋅ C
G_FB(f) = -_s---₍-¹-_f--₎--+--_â‹---^sR---⁽--₁-^f--⁾-_â‹--^â‹-₍--^RC-----²¹----^â‹_+---^C--_C---¹--₂----₎ ⋅
------------------------------¹-----+-----^s---⁽---^f--⁾---^â‹---⁽---^R----¹-----+-----^R----³----⁾---^â‹---^C-----³-------------------------------
(
1
+
s
(
f)
⋅
R₃
⋅
C₃
)
⋅



1
+
s
(
f
)
⋅
R₂
⋅



C^-C----₁^{-1----+⋅---C-}C^----2-₂^-_{}
G_CL(f) = G_MOD(f) ⋅ G_FB(f)
where, s(f) = 2π ⋅ f ⋅ j
As before when tieing VFF to VIN terms in the above
equations can be simplified as follows:
-^d---^M-----^A----^X-----^â‹---^V----^I--^N-- = -----¹-----^â‹---^V----^I--^N------- = 6.25
V_OSC
0.16 ⋅ V_IN
COMPENSATION BREAK FREQUENCY EQUATIONS
F_Z1
=
--------------¹----------------
2π ⋅ R₂ ⋅ C₁
F_Z2 = -₂---_π-----_â‹---₍---_R----₁----+-¹----_R-----₃---₎----_â‹---_C----₃--
F_P1
=
---------------------¹-----------------------
2π ⋅ R₂ ⋅ -_CC----₁-¹---+-^â‹---^C-_C----²-₂-
F_P2
=
--------------¹----------------
2π ⋅ R₃ ⋅ C₃
Figure 11 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual modulator gain has a high gain
peak dependent on the quality factor (Q) of the output filter,
which is not shown. Using the above guidelines should yield a
compensation gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at F_P2 against the capabilities of the error
amplifier. The closed loop gain, G_CL, is constructed on the
log-log graph of Figure 11 by adding the modulator gain,
G_MOD (in dB), to the feedback compensation gain, G_FB (in
dB). This is equivalent to multiplying the modulator transfer
function and the compensation transfer function and then
plotting the resulting gain.
F_Z1F_Z2 F_P1
F_P2
MODULATOR GAIN
COMPENSATION GAIN
CLOSED LOOP GAIN
OPEN LOOP E/A GAIN
20
log


RR-----21--_
0
20log -^d----^M-----^A-----^X-----^â‹----V----I--N---
V_OSC
G_FB
G_CL
LOG
F_LC F_CE F₀
G_MOD
FREQUENCY
FIGURE 11. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
17
FN9214.0
March 9, 2006