ISL6540_06 Datasheet, PDF (16/20 Pages) Intersil Corporation – Single-Phase Buck PWM Controller with Integrated High Speed MOSFET Driver and Pre-Biased Load Capability

ISL6540
Figure 8 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Minimize any leakage
current paths on the SS pin and locate the capacitor, C_SS
close to the SS pin (as described earlier) as the internal
current source is only 38µA. Provide local decoupling
between PVCC and PGND pins as described earlier. Locate
the capacitor, C_BOOT as close as practical to the BOOT and
PHASE pins.
Compensating the Converter
The ISL6540 single-phase converter is a voltage-mode
controller. This section highlights the design considerations for
a voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
network is recommended (see Figure 9).
C₂
R₂
C₁
COMP
C₃
R₁
R₃
FB
VMON
ISL6540
C₂
COMP
R₂
C₁
-
FB
E/A ⁺
VREF
R₃
C₃
R₁
VMON
R_FB
-
VSEN-
C_{SEN ROS}
+
VSEN+
PWM
CIRCUIT
OSCILLATOR
V_OSC
HALF-BRIDGE
DRIVE
V_OUT
V_IN
UGATE
PHASE
LGATE
L
DCR
C
ESR
FIGURE 9. COMPENSATION CONFIGURATION FOR ISL6540
WHEN USING DIFFERENTIAL REMOTE SENSE
Figure 10 highlights the voltage-mode control loop for a
synchronous-rectified buck converter, when using an internal
differential remote sense amplifier. The output voltage
(V_OUT) is regulated to the reference voltage, VREF, level.
The error amplifier output (COMP pin voltage) is compared
with the oscillator (OSC) triangle wave to provide a pulse-
width modulated wave with an amplitude of V_IN at the
PHASE node. The PWM wave is smoothed by the output
filter (L and C). The output filter capacitor bank’s equivalent
series resistance is represented by the series resistor ESR.
The modulator transfer function is the small-signal transfer
function of V_OUT/V_COMP. This function is dominated by a
DC gain, given by d_MAXV_IN/V_OSC, and shaped by the
output filter, with a double pole break frequency at F_LC and a
zero at F_CE. For the purpose of this analysis C and ESR
represent the total output capacitance and its equivalent
series resistance.
F_LC
=
-------------¹--------------
2π ⋅ L ⋅ C
F_CE
=
----------------¹-----------------
2π ⋅ C ⋅ ESR
ISL6540 EXTERNAL CIRCUIT
FIGURE 10. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The compensation network consists of the error amplifier
(internal to the ISL6540) and the external R₁-R₃, C₁-C₃
components. The goal of the compensation network is to
provide a closed loop transfer function with high 0dB crossing
frequency (F₀; typically 0.1 to 0.3 of F_SW) and adequate
phase margin (better than 45°). Phase margin is the
difference between the closed loop phase at F_0dB and 180°.
The equations that follow relate the compensation network’s
poles, zeros and gain to the components (R₁, R₂, R₃, C₁, C₂,
and C₃) in Figures 9 and 10. Use the following guidelines for
locating the poles and zeros of the compensation network:
1. Select a value for R₁ (1kΩ to 10kΩ, typically). Calculate
value for R₂ for desired converter bandwidth (F₀). If
setting the output voltage to be equal to the reference set
voltage as shown in Figure 22, the design procedure can
be followed as presented. However, when setting the
output voltage via a resistor divider placed at the input of
the differential amplifier (as shown in Figure 10), in order
to compensate for the attenuation introduced by the
resistor divider, the below obtained R₂ value needs be
multiplied by a factor of (R_OS+R_FB)/R_OS. The remainder
of the calculations remain unchanged, as long as the
compensated R₂ value is used.
16
FN9214.0
March 9, 2006