ISL6551 Datasheet, PDF (18/26 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
Current Sense
Q3_S
T_CURRENT
ISENSE
Q4_S
FIGURE 14A. TWO-LEG SENSE
V_INF
ISENSE
CURRENT_SEN_P
FIGURE 14B. TOP SENSE
Q3_S & Q4_S
RSENSE
ISENSE
FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL)
Two-Leg Sense - Senses the current that flows through both
lower primary FETs. Operates at the switching frequency.
Top Sense - Senses the sum of the current that flows through
both upper primary FETs. Operates at the clock frequency.
Resistor Sense - This simple scheme is used in a primary side
control system. The sum of the current that flows through both
lower primary FETs is sensed with a low impedance power
resistor. The sources of Q3 and Q4 and ISENSE should be tied
at the same point as close as possible.
BIASES
Linear Regulator - In a primary side control system, a
linear regulator derived from the input line can be used for
the start-up purpose, and an extra winding coupled with the
main transformer can provide the controller power after the
start up.
DCM Flyback - Use a PWM controller to develop both
primary and secondary biases with discontinuous current
mode flyback topology.
Primary FETs
V_INF
or CURRENT_SEN_P
Q1_G
P–
Q1
Q2_G
Q2
P+
Q3_G
Q3
Q4_G
Q4
Q3_S
Q4_S
FIGURE 15A. FULL BRIDGE
P1–
P2–
Q3_G
Q3
Q4_G
Q4
Q3_S
Q4_S
FIGURE 15B. PUSH-PULL
Full Bridge - Four MOSFETs are required for full bridge
converters. The drain to source voltage rating of the
MOSFETs is Vin.
Push-Pull - Only the two lower MOSFETs are required for
push-pull converters. The two upper drivers are not used.
The V_DS of the MOSFETs is 2xVin.
18
FN9066.4
July 8, 2005