ISL6551 Datasheet, PDF (15/26 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
• Power Good (DCOK)
- DCOK pin is an open drain output capable of sinking
5mA. It is low when the output voltage is within the
UVOV window. The static regulation limit is ±3%, while
the ±5% is the dynamic regulation limit. It indicates
power good when the EAI is within -3% to +5% on the
rising edge and within +3% to -5% on the falling edge, as
shown in Figure 11.
EAI
+5%
+3%
EANI
-3%
-5%
DCOK
FAULT
FIGURE 11. UNDERVOLTAGE-OVERVOLTAGE WINDOW
- The DCOK comparator might not be triggered even
though the output voltage exceeds ± 5% limits at load
transients. This is because the feedback network of the
error amplifier filters out part of the transients and the EAI
only sees the remaining portion that is still within the limits,
as illustrated in Figure 12. The lower the “zero (1/RC)” of
the error amplifier, the larger the portion of the transient is
filtered out.
18K
15N
EAI R
C
VOUT
-
1K _{EANI +}
EAO
1.10V
1.00V
VOUT
0.90V
1.05V
EAI
1.00V
0.95V
FIGURE 12. OUTPUT TRANSIENT REJECTION
• Thermal Pad (in QFN only)
- In the QFN package, the pad underneath the center of
the IC is a “floating” thermal substrate. The PCB
“thermal land” design for this exposed die pad should
include thermal vias that drop down and connect to
one or more buried copper plane(s). This combination
of vias for vertical heat escape and buried planes for
heat spreading allows the QFN to achieve its full
thermal potential. This pad should be connected to a
low noise copper plane such as Vss.
- Refer to TB389 for design guidelines.
15
FN9066.4
July 8, 2005