ISL6551 Datasheet, PDF (16/26 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
Additional Applications Information
Table 1 highlights parameter setting for the ISL6551.
Designers can use this table as a design checklist. For
detailed operation of the ISL6551, see Block/Pin Functional
Descriptions.
TABLE 1. PARAMETER SETTING HIGHLIGHTS/CHECKLIST
VDD = 12V at room temperature, unless otherwise stated.
PARAMETER
PIN NAME
FORMULA OR SETTING HIGHLIGHT
UNIT FIGURE #
Frequency
CT
Set 50% Duty Cycle Pulses with a fixed frequency
kHz
1, 2
Dead Time
RD
DT = M x RD/kΩ, where M = 11.4
ns
3
Resonant Delay
Ramp Adjust
R_RESDLY
R_RA
t_RESDLY = 4.01 x R_RESDLY/kΩ + 13
Vramp = BGREF/(R_RA x 500E-12) x dt
ns
7
V
-
Current Sense
ISENSE
<Vclamp-200mV-Vramp
V
-
Peak Current
PKILIM
<BGREF and slightly higher than Vclamp
V
6
Bandgap Reference
BGREF
1.263V ±2%, 399kΩ pull-up, No more than 100µA load
V
-
Leading Edge Blanking
Current Share Compensation
R_LEB
CS_COMP
t_LEB = 2 x R_LEB/kΩ + 15, never leave it floating
0.1µ for a low current loop bandwidth (100 - 500Hz)
ns
8, 9
Hz
10
Soft-Start & Output Rise Time
Clamp Voltage (Vclamp)
CSS
CSS
t_ss = Vclamp x Css/Iss, t_rise = EANI x CSS / Iss, Iss = 10µA ±20% S
4
Vclamp = Iss x Rcss, or Reference-based clamp
V
4, 5
Error Amplifier
EANI, EAI, EAO EANI, EAO < Vclamp
V
-
Share Support
SHARE
30K load & a resistor (1K, typ.) between EANI and OUTPUT REF. -
-
Latching Shutdown
LATSD
Latch IC off at > 3V
V
-
Power Good
DCOK
±5% with hysteresis, Sink up to 5mA, transient rejection
V
11, 12
IC Enable
ON/OFF
Turn on/off at TTL level
V
-
Reference Ground
VSS
Connect to PGND in only one single point
-
-
Power Ground
PGND
Single point to VSS plane
-
-
Upper Drivers
UPPER1, UPPER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
-
Lower Drivers
LOWER1, LOWER2 Capacitive load up to 1.6nF at Fsw = 500kHz
-
-
Synchronous Drive Signals
SYNC1, SYNC2 Capacitive load up to 20pF at Fsw = 500kHz
-
-
Bias for Control Circuits
VDD
12V ±10%, 0.1µF decoupling capacitor
V
-
Biases for Bridge Drivers
VDDP1, VDDP2 Need decoupling capacitors
V
-
16
FN9066.4
July 8, 2005