ISL6551 Datasheet, PDF (10/26 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
Block/Pin Functional Descriptions
Detailed descriptions of each individual block in the functional
block diagram on page 3 are included in this section.
Application information and design considerations for each pin
and/or each block are also included.
• IC Bias Power (VDD, VDDP1, VDDP2)
- The IC is powered from a 12V ± 10% supply.
- VDD supplies power to both the digital and analog circuits
and should be bypassed directly to the VSS pin with an
0.1µF low ESR ceramic capacitor.
- VDDP1 and VDDP2 are the bias supplies for the upper
drivers and the lower drivers, respectively. They should be
decoupled with ceramic capacitors to the PGND pin.
- Heavy copper should be attached to these pins for a better
heat spreading.
• IC GNDs (VSS, PGND)
- VSS is the reference ground, the return of VDD, of all
control circuits and must be kept away from nodes with
switching noises. It should be connected to the PGND in
only one location as close to the IC as practical. For a
secondary side control system, it should be connected to
the net after the output capacitors, i.e., the output return
pinout(s). For a primary side control system, it should be
connected to the net before the input capacitors, i.e., the
input return pinout(s).
- PGND is the power return, the high-current return path of
both VDDP1 and VDDP2. It should be connected to the
SOURCE pins of two lower power switches or the
RETURNs of external drivers as close as possible with
heavy copper traces.
- Copper planes should be attached to both pins.
• Undervoltage Lockout (UVLO)
- UVLO establishes an orderly start-up and verifies that VDD
is above the turn-on threshold voltage (VDD_ON). All the
drivers are held low during the lockout. UVLO incorporates
hysteresis VDD_HYS to prevent multiple startup/shutdowns
while powering up.
- UVLO limits are not applicable to VDDP1 and VDDP2.
• Bandgap Reference (BGREF)
- The reference voltage VREF is generated by a precision
bandgap circuit.
- This pin must be pulled up to VDD with a resistance of
approximately 399kΩ for proper operation. For additional
reference loads (no more than 1mA), this pull-up resistor
should be scaled accordingly.
- This pin must also be decoupled with an 0.1µF low ESR
ceramic capacitor.
• Clock Generator (CT, RD)
- This free-running oscillator is set by two external
components as shown in Figure 1. A capacitor at CT is
charged and discharged with two equal constant current
sources and fed into a window comparator to set the clock
frequency. A resistor at RD sets the clock dead time. RD
and CT should be tied to the VSS pin on their other ends
as close as possible. The corresponding CT for a particular
frequency can be selected from Figure 2.
- The switching frequency (Fsw) of the power train is half of
the clock frequency (Fclock), as shown in Equation 1.
Fsw
=
F_-----c_---l_--o_----c_---k_--
2
(EQ. 1)
RD
SET CLOCK
DEAD TIME (DT)
RD
VDD-
I_CT
VMAX
- ^OUT
+
CLK
CT
S
Q
Q
CT
VMIN
- ^OUT
+
RQ
Q
I_CT
CLK
DT
DT
FIGURE 1. SIMPLIFIED CLOCK GENERATOR CIRCUIT
10
FN9066.4
July 8, 2005