ISL6551 Datasheet, PDF (13/26 Pages) Intersil Corporation – ZVS Full Bridge PWM Controller

ISL6551
500
+18%
450
-24%
400
350
300
250
200
150
100 ^+37%
+4%
50
0
20
40
60
80
100 120
R_RESDLY (kΩ)
FIGURE 7. R_RESDLY vs RESDLY
• Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent
false triggering, the leading edge of the sensed current
signal is blanked out by a period that can be programmed
with the R_LEB resistor. Internal switches gate the analog
input to the PWM comparator, implementing the blanking
function that eliminates response degrading delays which
would be caused if filtering of the current feedback was
incorporated. The current ramp is blanked out during the
resonant delay period because no switching occurs in the
lower FETs. The leading edge blanking function will not be
activated until the soft-start (CSS) reaches over 400mV, as
illustrated in Figures 4 and 9. The leading edge blanking
(LEB) function can be disabled by tying the R_LEB pin to
VDD, i.e., LEB=1. Never leave the pin floating.
- The blanking time can be estimated with Equation 9,
whose relationship can be seen in Figure 8. The
percentages in the figure are the tolerances at the two
endpoints of the curve.
t_LEB = 2 x R_LEB / kΩ + 15 (ns)
(EQ. 9)
300
250
200
150
100 +51%
50 ^-11%
0
20
40
60
80
100
R_LEB (kΩ)
FIGURE 8. R_LEB vs t_LEB
+20%
-18%
120
140
VDD
0.1µ
399K
R_RA
BGREF
R_RA
ISENSE
ADD RAMP
ADJ_RAMP
+
-
200mV
R_LEB
R_LEB
SET
BLANKING
TIME
RESDLY
LEB
SSL
(See Fig. 4)
ADJ_RAMP
200mV
RAMP_OUT
(TO PWM
ISENSE
0
COMPARATOR)
RAMP_OUT
200mV
BLANK
RESDLY
0
X
1
1
LEB
X
0
1
X
SSL RAMP_OUT
X
BLANK
0
BLANK
X
NO BLANK
1
NO BLANK
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
13
FN9066.4
July 8, 2005