ISL6261A Datasheet, PDF (18/34 Pages) Intersil Corporation – Single-Phase Core Regulator for IMVP-6 Mobile CPUs

ISL6261A
These traces should be laid out as noise sensitive traces.
For optimum load line regulation performance, the traces
connecting these two pins to the Kelvin sense leads of the
processor should be laid out away from rapidly rising voltage
nodes (switching nodes) and other noisy traces. Common
mode and differential mode filters are recommended as
shown in Figure 6. The recommended filter resistance range
is 0~10Ω so it does not interact with the 50k input resistance
of the differential amplifier. The filter resistor may be inserted
between VCC-SENSE and the VSEN pin. Another option is
to place one between VCC-SENSE and the VSEN pin and
another between VSS-SENSE and the RTN pin. The need of
these filters also depends on the actual board layout and the
noise environment.
Since the voltage feedback is sensed at the processor die, if
the CPU is not installed, the regulator will drive the output
voltage all the way up to damage the output capacitors due
to lack of output voltage feedback. Ropn1 and Ropn2 are
recommended, as shown in Figure 6, to prevent this
potential issue. Ropn1 and Ropn2, typically ranging
20~100Ω, provide voltage feedback from the regulator local
output in the absence of the CPU.
Setting the Switching Frequency - FSET
The R³ modulator scheme is not a fixed frequency PWM
architecture. The switching frequency increases during the
application of a load to improve transient performance.
It also varies slightly depending on the input and output
voltages and output current, but this variation is normally
less than 10% in continuous conduction mode.
Resistor R_fset (R₇ in Figure 2), connected between the VW
and COMP pins of the ISL6261A, sets the synthetic ripple
window voltage, and therefore sets the switching frequency.
This relationship between the resistance and the switching
frequency in CCM is approximately given by Equation 5.
R _fset (kΩ) = ( period(μs) − 0.29)× 2.33
(EQ. 5)
In diode emulation mode, the ISL6261A stretches the
switching period. The switching frequency decreases as the
load becomes lighter. Diode emulation mode reduces the
switching loss at light load, which is important in conserving
battery power.
Voltage Regulator Thermal Throttling
lntel^® IMVP-6^® technology supports thermal throttling of the
processor to prevent catastrophic thermal damage to the
voltage regulator. The ISL6261A features a thermal monitor
sensing the voltage across an externally placed negative
temperature coefficient (NTC) thermistor. Proper selection
and placement of the NTC thermistor allows for detection of
a designated temperature rise by the system.
54µA
6µA
NTC
SW1
Internal to
ISL6261A
V
NTC
R _NTC
RS
1.23V
SW2
1.20V
VR_TT#
FIGURE 7. CIRCUITRY ASSOCIATED WITH THE THERMAL
THROTTLING FEATURE
Figure 7 shows the circuitry associated with the thermal
throttling feature of the ISL6261A. At low temperature, SW1
is on and SW2 connects to the 1.20V side. The total current
going into the NTC pin is 60µA. The voltage on the NTC pin
is higher than 1.20V threshold voltage and the comparator
output is low. VR_TT# is pulled up high by an external
resistor. Temperature increase will decrease the NTC
thermistor resistance. This decreases the NTC pin voltage.
When the NTC pin voltage drops below 1.2V, the comparator
output goes high to pull VR_TT# low, signaling a thermal
throttle. In addition, SW1 turns off and SW2 connects to
1.23V, which decreases the NTC pin current by 6uA and
increases the threshold voltage by 30mV. The VR_TT#
signal can be used by the system to change the CPU
operation and decrease the power consumption. As the
temperature drops, the NTC pin voltage goes up. If the NTC
pin voltage exceeds 1.23V, VR_TT# will be pulled high.
Figure 8 illustrates the temperature hysteresis feature of
VR_TT#. T₁ and T₂ (T₁>T₂) are two threshold temperatures.
VR_TT# goes low when the temperature is higher than T₁
and goes high when the temperature is lower than T₂.
VR_TT#
Logic_1
Logic_0
T₂ T₁
T (^oC)
FIGURE 8. VR_TT# TEMPERATURE HYSTERISIS
18
FN6354.3
November 5, 2009