ISL6261A Datasheet, PDF (12/34 Pages) Intersil Corporation – Single-Phase Core Regulator for IMVP-6 Mobile CPUs

ISL6261A
Theory of Operation
The ISL6261A is a single-phase regulator implementing
Intel^® IMVP-6^® protocol and includes an integrated gate
driver for reduced system cost and board area. The
ISL6261A IMVP-6^® solution provides optimum steady state
and transient performance for microprocessor core voltage
regulation applications up to 25A. Implementation of Diode
Emulation Mode (DEM) operation further enhances system
efficiency.
The heart of the ISL6261A is the patented R³ Technology™,
Intersil’s Robust Ripple Regulator modulator. The R³â„¢
modulator combines the best features of fixed frequency and
hysteretic PWM controllers while eliminating many of their
shortcomings. The ISL6261A modulator internally
synthesizes an analog of the inductor ripple current and
uses hysteretic comparators on those signals to establish
PWM pulses. Operating on the large-amplitude and noise-
free synthesized signals allows the ISL6261A to achieve
lower output ripple and lower phase jitter than either
conventional hysteretic or fixed frequency PWM controllers.
Unlike conventional hysteretic converters, the ISL6261A has
an error amplifier that allows the controller to maintain 0.5%
voltage regulation accuracy throughout the VID range from
0.75V to 1.5V.
The hysteretic window voltage is with respect to the error
amplifier output. Therefore the load current transient results
in increased switching frequency, which gives the R³â„¢
regulator a faster response than conventional fixed
frequency PWM regulators.
Start-up Timing
With the controller’s VDD pin voltage above the POR
threshold, the start-up sequence begins when VR_ON
exceeds the 3.3V logic HIGH threshold. In approximately
100μs, SOFT and VO start ramping to the boot voltage of
1.2V. At start-up, the regulator always operates in
Continuous Current Mode (CCM), regardless of the control
signals. During this interval, the SOFT cap is charged by a
41μA current source. If the SOFT capacitor is 20nF, the
SOFT ramp will be 2mV/µs for a soft-start time of 600µs.
Once VO is within 20mV of the boot voltage the ISL6261A
will count 13 clock cycles, then pull CLK_EN# low, and
charge/discharge the SOFT cap with approximately 200µA,
therefore VO slews at 10mV/µs to the voltage set by the VID
pins. In approximately 7ms, PGOOD is asserted HIGH.
Figure 4 shows typical start-up timing.
Static Operation
After the start-up sequence, the output voltage will be
regulated to the value set by the VID inputs per Table 1,
which is presented in the lntel^® IMVP-6^® specification. The
ISL6261A regulates the output voltage with ±0.5% accuracy
over the range of 0.7V to 1.5V.
VDD
VR_ON
100µs
SOFT &VO
20mV
10mV/µs
Vboot
13xT_s
2mV/µs
CLK_EN#
IMVP-VI PGOOD
~7ms
FIGURE 4. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
A true differential amplifier remotely senses the core voltage
to precisely control the voltage at the microprocessor die.
VSEN and RTN pins are the inputs to the differential
amplifier.
As the load current increases from zero, the output voltage
droops from the VID value proportionally to achieve the
IMVP-6^® load line. The ISL6261A can sense the inductor
current through the intrinsic series resistance of the
inductors, as shown in Figure 2, or through a precise resistor
in series with the inductor, as shown in Figure 3. The
inductor current information is fed to the VSUM pin, which is
the non-inverting input to the droop amplifier. The DROOP
pin is the output of the droop amplifier, and DROOP-VO
voltage is a high-bandwidth analog representation of the
inductor current. This voltage is used as an input to a
differential amplifier to achieve the IMVP-6^® load line, and
also as the input to the overcurrent protection circuit.
The PMON pin is the power monitor output. The voltage
potential on this pin (V_PMON) is given by V_PMON = 35x(V_SEN-
V_RTN)x(V_DROOP-V_O). Since V_SEN-V_RTN is the CPU voltage
and V_DROOP-V_O represents the inductor current, V_PMON is
an analog voltage indicating the power consumed by the
CPU. V_PMON has high bandwidth so it represents the
instantaneous power including the pulsation caused inductor
current switching ripple. The maximum available V_PMON is
approximately 3V.
When using inductor DCR current sensing, an NTC
thermistor is used to compensate the positive temperature
coefficient of the copper winding resistance to maintain the
load-line accuracy.
The switching frequency of the ISL6261A controller is set by
the resistor R_FSET between pins VW and COMP, as shown in
Figures 2 and 3.
12
FN6354.3
November 5, 2009