X96010 Datasheet, PDF (13/26 Pages) Intersil Corporation – Sensor Conditioner with Dual Look Up Table Memory and DACs

X96010
L2DAS: LUT2 DIRECT ACCESS SELECT BIT (NON-
VOLATILE)
When bit L2DAS is set to “0” (default), LUT2 is
addressed by the output of the on-chip A/D converter.
When bit L2DAS is set to “1”, LUT2 is addressed by
bits L2DA5 - L2DA0.
D2DAS: D/A 2 DIRECT ACCESS SELECT BIT (NON-
VOLATILE)
When bit D2DAS is set to “0” (default), the input to the
D/A converter 2 is a row of LUT2. When bit D2DAS is set
to “1”, that input is the content of the Control register 4.
Control Register 6
This register is accessed by performing a Read or
Write operation to address 86h of memory.
WEL: WRITE ENABLE LATCH (VOLATILE)
The WEL bit controls the Write Enable status of the
entire X96010 device. This bit must be set to “1” before
any other Write operation (volatile or nonvolatile). Oth-
erwise, any proceeding Write operation to memory is
aborted and no ACK is issued after a Data Byte.
The WEL bit is a volatile latch that powers up in the “0”
state (disabled). The WEL bit is enabled by writing
10000000₂ to Control register 6. Once enabled, the
WEL bit remains set to “1” until the X96010 is powered
down, and then up again, or until it is reset to “0” by
writing 00000000₂ to Control register 6.
A Write operation that modifies the value of the WEL bit
will not cause a change in other bits of Control register 6.
Status Register - ADC Output
This register is accessed by performing a Read opera-
tion to address 87h of memory.
AD7 - AD0: A/D CONVERTER OUTPUT BITS (READ
ONLY)
These eight bits are the binary output of the on-chip
A/D converter. The output is 00000000₂ for minimum
input and 11111111₂ for full scale input. The six
MSBs select a row of the LUTs.
13
FN8214.1
October 25, 2005