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X28HC64_06 Datasheet, PDF (11/17 Pages) Intersil Corporation – 5 Volt, Byte Alterable EEPROM
X28HC64
SYSTEM CONSIDERATIONS
Because the X28HC64 is frequently used in large
memory arrays, it is provided with a two-line control
architecture for both read and write operations. Proper
usage can provide the lowest possible power dissipa-
tion, and eliminate the possibility of contention where
multiple I/O pins share the same bus.
To gain the most benefit, it is recommended that CE
be decoded from the address bus, and be used as the
primary device selection input. Both OE and WE would
then be common among all devices in the array. For a
read operation, this assures that all deselected
devices are in their standby mode, and that only the
selected device(s) is/are outputting data on the bus.
Because the X28HC64 has two power modes,
standby and active, proper decoupling of the memory
array is of prime concern. Enabling CE will cause tran-
sient current spikes. The magnitude of these spikes is
dependent on the output capacitive loading of the I/Os.
Therefore, the larger the array sharing a common bus,
the larger the transient spikes. The voltage peaks
associated with the current transients can be sup-
pressed by the proper selection and placement of
decoupling capacitors. As a minimum, it is recom-
mended that a 0.1µF high frequency ceramic capacitor
be used between VCC and VSS at each device.
Depending on the size of the array, the value of the
capacitor may have to be larger.
In addition, it is recommended that a 4.7µF electrolytic
bulk capacitor be placed between VCC and VSS for
each eight devices employed in the array. This bulk
capacitor is employed to overcome the voltage droop
caused by the inductive effects of the PC board traces.
Normalized ICC(RD) by Temperature
Over Frequency
1.4
5.5 VCC
1.2
- 55°C
+ 25°C
1.0
+ 125°C
0.8
0.6
0.4
0.2
0
10
20
Frequency (MHz)
Normalized ICC(RD) @ 25% Over
the VCC Range and Frequency
1.4
1.2
1.0
0.8
5.5 VCC
5.0 VCC
4.5 VCC
0.6
0.4
0.2
0
10
20
Frequency (MHz)
11
FN8109.1
June 7, 2006