82546GB Datasheet, PDF (9/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
ERRATA
1. LSO Premature Descriptor Write Back
Problem:
Implication:
Workaround:
Status:
For large send fetches ONLY (not normal or jumbo frames) the internal DMA engine will decompose the large-
send data fetch into a series of individual requests that are completed sequentially. When all read data
associated with the first internal DMA request has been fetched, the descriptor is flagged as ready for
writeback. Though all data associated with the entire LSO descriptor will eventually be fetched, the descriptor
writeback may occur prematurely. The device should wait until all bytes associated with the data descriptor
have been completely fetched before writing back the transmit descriptor.
Due to premature write back, an operating system may release and reallocate the buffer, potentially causing
buffer re-use and transmission of incorrect data.
Utilize a second descriptor to point to the last four bytes of the large-send transmit data, and ensure that the
buffer is not freed to the operating system/application until the second descriptor has been marked as complete
via a status writeback operation.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
2. XOFF from Link Partner can Pause Flow-Control (XON/XOFF) Transmission
Problem:
Implication:
Workaround:
Status:
When the 82546GB transmitter is paused (by having received an XOFF from link partner), not only is the
transmit of normal packets paused, but also of outbound XON/XOFF frames resulting from Receive Packet
Buffer levels and Flow-Control Thresholds. Normally, partner’s XOFF packets only pause the LAN controller for
a finite time interval, after which outbound XON/XOFF’s due to Receive Packet-Buffer fullness are again
permitted to be sent.
If the transmitter is paused when a Receive FIFO XOFF threshold is reached, the transmission of XOFF frames
does not occur and Receive FIFO overrun may potentially occur, resulting in lost packets. This is only expected
to be seen with an abnormally high pause time from link partner’s XOFF packet(s).
Receive Flow-Control Thresholds may be tuned/lowered based on the expected maximum pause interval
expected from link partner’s XOFF packet in order to minimize the likelihood of Receive FIFO overruns.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
3. Transmit Descriptor use of RS for non-data (Context & Null) Descriptors
Problem:
Implication:
Workaround:
Status:
Due to an internal logic error in the descriptor internal queue, if the internal descriptor queue becomes
completely full of pending descriptor status writebacks, the descriptor logic may issue a writeback request with
an incorrect writeback amount. The internal descriptor queue may accumulate pending writebacks if transmit
descriptors that do not directly refer to transmit data buffers (e.g. context or Null descriptors) are submitted with
a status-writeback request (RS asserted) and legacy writeback (status byte writeback only) is utilized.
Due to the invalid internal writeback request size, the PCI logic may hang.
Ensure that status-writeback reporting (RS) is not set on context or Null descriptors. Alternatively, utilize full-
descriptor writebacks (TXDCTL.WTHRESH >= 1). The former workaround is the recommended alternative.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
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