82546GB Datasheet, PDF (14/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
15. PCI-X Burst Write Transactions to Memory Mapped Registers at Non-Qword-
Aligned Offsets Fail
Problem:
The device does not properly handle burst (greater than 4 bytes in length) write transactions to its memory
mapped register space. Registers with addresses ending in 0x0 or 0x8 work, but registers with addresses
ending in 0x4 or 0xC cannot be written. For example, a PCI-X Memory Write Block transaction writing 16 bytes
to offset 0x2800 properly writes to locations 0x2800 and 0x2808; however, locations 0x2804 and 0x2808 are
not updated.
Implication:
The specification for the device states that memory-mapped registers should only be written 32 bits at a time.
Software should always be written to follow this rule. It is particularly important during initialization when most
of the memory-mapped register accesses take place. Unfortunately, some platforms might perform write
combining, which turn consecutive 32-bit writes into a single burst transaction. In this case, the registers with
addresses ending in 0x4 or 0xC are not written. Common areas for consecutive adjacent register writes include
setup of the large register arrays (MTA, VFTA, and RAR).
Workaround: If there is platform-level control for a write-combining feature, turn it off.
Alternately, software can be written with the possibility of write combining in mind:
• Writes to consecutive registers can be followed by a read transaction, which should flush the posted write
from any bridge that might perform combining.
• Initialization of large register arrays (VFTA, MTA) can be performed in reverse, writing the highest location
first and working backward to the lowest. This prevents write combining from occurring since the writes no
longer meet the rules that allow combining.
Status:
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
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