82546GB Datasheet, PDF (11/16 Pages) Intel Corporation – Gigabit Ethernet Controller Specification Update

82546GB GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
6. Wakeup Packet Memory (WUPM) cleared upon reset
Problem:
Implication:
Workaround:
Status:
The 82546GB specifications state that the Wakeup Packet Memory (WUPM) is not cleared on any reset. This
is incorrect. Any reset or power-state transition will clear the contents of these registers.
Because a power-state transition takes place on wakeup, the Wakeup Packet Memory will always be cleared
before it can be read by software. This makes the memory effectively unable to provide the capability for
inspecting the wakeup packet content.
There is no workaround. WUPM will be considered to be defeatured for the affected controllers.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
7. Unexpected RMCP ACK packets in ASF mode
Problem:
Implication:
Workaround:
Status:
According to the RMCP protocol, the response to all RMCP commands (except ACK) should be an RMCP ACK
packet. In ASF mode, the Ethernet Controller responds to RMCP ACK packets with a second ACK.
Any management software should be aware of this behavior and not respond to the additional RMCP ACK
packets.
None.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
8. Exceeding PCI Power Management Specification Limit of 375mA current
during reset and power state transitions
Problem:
Implication:
Workaround:
Status:
During resets and power state transitions the controller may briefly draw more than 375 mA of current as the
digital signal processors in the PHY attempt to converge. The excessive current draw persists for approximately
100 milliseconds. Refer to the "Power Specifications -- MAC/PHY" section of this document for specific values.
If an application has current limiting circuitry in place, the Ethernet Controller may trigger these safeguards in
power-up or during transitions between D0 and D3 power states.
None.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
9. Inbound and Outbound reads not fully decoupled in PCI-X mode
Problem:
Implication:
If the Ethernet controller receives a read as a target and signals a split response it will not deliver a completion
to this read until its entire outstanding read requests have been satisfied. The device should not make the
completion of a sequence for which it is the completer contingent upon another device completing a sequence
for which it is a requester.
There is a slight system performance impact due to this erratum. Processors may be stalled while the read
transaction is outstanding, so the extra delay may adversely affect CPU utilization.
Workaround:
Status:
If and only if a host bridge also has a similar dependency, the possibility of a deadlock exists. A situation may
arise where the bridge is waiting for the controller to respond to a DWord read while the controller is waiting for
the bridge to complete a block read.
None.
Intel does not plan to resolve this erratum in a future stepping of the 82546GB Gigabit Ethernet Controller.
11